count60.vhd

来自「很好的多功能数字钟的HDL代码不可多得的哦」· VHDL 代码 · 共 47 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count60 is
  port(cout:out std_logic;
       en:in std_logic;
       qout1,qout2:out std_logic_vector(3 downto 0);
       clk,clr:in std_logic);
end count60;
architecture a of count60 is
  signal cin:std_logic;
begin 
process(clk,clr)
  variable cnt0:std_logic_vector(3 downto 0);
begin
 if clr='1'then
 cnt0:="0000";
 elsif clk'event and clk='1'then
   if (en='1')then
   if cnt0="1001"then
      cin<='1' ;
      cnt0:="0000";
   else cnt0:=cnt0+1; cin<='0';
    end if;
  end if;
 end if;
  qout2<=cnt0;
 end process;
process (clk,clr,cin)
  variable cnt1: std_logic_vector(3 downto 0);
begin
 if clr='1'then
   cnt1:="0000";
 elsif clk'event and clk='1'then
    if cin='1'then
      if cnt1="0101"then
        cnt1:="0000";cout<='1';
       else cnt1:=cnt1+1; cout<='0';
     end if;
    end if;
   else cnt1:=cnt1;
  end if;
qout1<=cnt1;
end process;
end a;