prev_cmp_max_and_min.tan.qmsg

基于CPLD的签到器的设计

{ "Info" "ITDB_FULL_TCO_RESULT" "button_judge row1\[9\] t1\[9\] 9.997 ns register " "Info: tco from clock \"button_judge\" to destination pin \"row1\[9\]\" through register \"t1\[9\]\" is 9.997 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "button_judge source 3.819 ns + Longest register " "Info: + Longest clock path from clock \"button_judge\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns button_judge 1 CLK PIN_18 42 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 42; CLK Node = 'button_judge'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "" { button_judge } "NODE_NAME" } } { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns t1\[9\] 2 REG LC_X10_Y8_N5 1 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X10_Y8_N5; Fanout = 1; REG Node = 't1\[9\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { button_judge t1[9] } "NODE_NAME" } } { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { button_judge t1[9] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { button_judge {} button_judge~combout {} t1[9] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.802 ns + Longest register pin " "Info: + Longest register to pin delay is 5.802 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns t1\[9\] 1 REG LC_X10_Y8_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y8_N5; Fanout = 1; REG Node = 't1\[9\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "" { t1[9] } "NODE_NAME" } } { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.480 ns) + CELL(2.322 ns) 5.802 ns row1\[9\] 2 PIN PIN_78 0 " "Info: 2: + IC(3.480 ns) + CELL(2.322 ns) = 5.802 ns; Loc. = PIN_78; Fanout = 0; PIN Node = 'row1\[9\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "5.802 ns" { t1[9] row1[9] } "NODE_NAME" } } { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 40.02 % ) " "Info: Total cell delay = 2.322 ns ( 40.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.480 ns ( 59.98 % ) " "Info: Total interconnect delay = 3.480 ns ( 59.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "5.802 ns" { t1[9] row1[9] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "5.802 ns" { t1[9] {} row1[9] {} } { 0.000ns 3.480ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { button_judge t1[9] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { button_judge {} button_judge~combout {} t1[9] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "5.802 ns" { t1[9] row1[9] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "5.802 ns" { t1[9] {} row1[9] {} } { 0.000ns 3.480ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "t1\[0\] judge0_origin\[0\] button_judge -1.271 ns register " "Info: th for register \"t1\[0\]\" (data pin = \"judge0_origin\[0\]\", clock pin = \"button_judge\") is -1.271 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "button_judge destination 3.819 ns + Longest register " "Info: + Longest clock path from clock \"button_judge\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns button_judge 1 CLK PIN_18 42 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 42; CLK Node = 'button_judge'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "" { button_judge } "NODE_NAME" } } { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns t1\[0\] 2 REG LC_X9_Y8_N7 1 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X9_Y8_N7; Fanout = 1; REG Node = 't1\[0\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { button_judge t1[0] } "NODE_NAME" } } { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { button_judge t1[0] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { button_judge {} button_judge~combout {} t1[0] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.311 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.311 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns judge0_origin\[0\] 1 PIN PIN_58 7 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_58; Fanout = 7; PIN Node = 'judge0_origin\[0\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "" { judge0_origin[0] } "NODE_NAME" } } { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.996 ns) + CELL(1.183 ns) 5.311 ns t1\[0\] 2 REG LC_X9_Y8_N7 1 " "Info: 2: + IC(2.996 ns) + CELL(1.183 ns) = 5.311 ns; Loc. = LC_X9_Y8_N7; Fanout = 1; REG Node = 't1\[0\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "4.179 ns" { judge0_origin[0] t1[0] } "NODE_NAME" } } { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.315 ns ( 43.59 % ) " "Info: Total cell delay = 2.315 ns ( 43.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.996 ns ( 56.41 % ) " "Info: Total interconnect delay = 2.996 ns ( 56.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "5.311 ns" { judge0_origin[0] t1[0] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "5.311 ns" { judge0_origin[0] {} judge0_origin[0]~combout {} t1[0] {} } { 0.000ns 0.000ns 2.996ns } { 0.000ns 1.132ns 1.183ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { button_judge t1[0] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { button_judge {} button_judge~combout {} t1[0] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "5.311 ns" { judge0_origin[0] t1[0] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "5.311 ns" { judge0_origin[0] {} judge0_origin[0]~combout {} t1[0] {} } { 0.000ns 0.000ns 2.996ns } { 0.000ns 1.132ns 1.183ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "131 " "Info: Allocated 131 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 31 11:44:24 2008 " "Info: Processing ended: Thu Jul 31 11:44:24 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}