prev_cmp_max_and_min.tan.qmsg

基于CPLD的签到器的设计

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "button_judge " "Info: Assuming node \"button_judge\" is an undefined clock" {  } { { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 8 -1 0 } } { "e:/study/cpld1/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/study/cpld1/quartus/bin/Assignment Editor.qase" 1 { { 0 "button_judge" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "button_judge register register t2\[0\] t2\[0\] 304.04 MHz Internal " "Info: Clock \"button_judge\" Internal fmax is restricted to 304.04 MHz between source register \"t2\[0\]\" and destination register \"t2\[0\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 3.289 ns " "Info: fmax restricted to clock pin edge rate 3.289 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.197 ns + Longest register register " "Info: + Longest register to register delay is 2.197 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns t2\[0\] 1 REG LC_X9_Y7_N8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y7_N8; Fanout = 2; REG Node = 't2\[0\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "" { t2[0] } "NODE_NAME" } } { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.914 ns) + CELL(0.200 ns) 1.114 ns t2~4205 2 COMB LC_X9_Y7_N5 1 " "Info: 2: + IC(0.914 ns) + CELL(0.200 ns) = 1.114 ns; Loc. = LC_X9_Y7_N5; Fanout = 1; COMB Node = 't2~4205'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "1.114 ns" { t2[0] t2~4205 } "NODE_NAME" } } { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.803 ns) + CELL(0.280 ns) 2.197 ns t2\[0\] 3 REG LC_X9_Y7_N8 2 " "Info: 3: + IC(0.803 ns) + CELL(0.280 ns) = 2.197 ns; Loc. = LC_X9_Y7_N8; Fanout = 2; REG Node = 't2\[0\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "1.083 ns" { t2~4205 t2[0] } "NODE_NAME" } } { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.480 ns ( 21.85 % ) " "Info: Total cell delay = 0.480 ns ( 21.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.717 ns ( 78.15 % ) " "Info: Total interconnect delay = 1.717 ns ( 78.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "2.197 ns" { t2[0] t2~4205 t2[0] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "2.197 ns" { t2[0] {} t2~4205 {} t2[0] {} } { 0.000ns 0.914ns 0.803ns } { 0.000ns 0.200ns 0.280ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "button_judge destination 3.819 ns + Shortest register " "Info: + Shortest clock path from clock \"button_judge\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns button_judge 1 CLK PIN_18 42 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 42; CLK Node = 'button_judge'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "" { button_judge } "NODE_NAME" } } { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns t2\[0\] 2 REG LC_X9_Y7_N8 2 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X9_Y7_N8; Fanout = 2; REG Node = 't2\[0\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { button_judge t2[0] } "NODE_NAME" } } { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { button_judge t2[0] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { button_judge {} button_judge~combout {} t2[0] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "button_judge source 3.819 ns - Longest register " "Info: - Longest clock path from clock \"button_judge\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns button_judge 1 CLK PIN_18 42 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 42; CLK Node = 'button_judge'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "" { button_judge } "NODE_NAME" } } { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns t2\[0\] 2 REG LC_X9_Y7_N8 2 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X9_Y7_N8; Fanout = 2; REG Node = 't2\[0\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { button_judge t2[0] } "NODE_NAME" } } { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { button_judge t2[0] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { button_judge {} button_judge~combout {} t2[0] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { button_judge t2[0] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { button_judge {} button_judge~combout {} t2[0] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { button_judge t2[0] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { button_judge {} button_judge~combout {} t2[0] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "2.197 ns" { t2[0] t2~4205 t2[0] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "2.197 ns" { t2[0] {} t2~4205 {} t2[0] {} } { 0.000ns 0.914ns 0.803ns } { 0.000ns 0.200ns 0.280ns } "" } } { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { button_judge t2[0] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { button_judge {} button_judge~combout {} t2[0] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { button_judge t2[0] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { button_judge {} button_judge~combout {} t2[0] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "" { t2[0] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { t2[0] {} } {  } {  } "" } } { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 26 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "t1\[9\] judge2_origin\[3\] button_judge 11.164 ns register " "Info: tsu for register \"t1\[9\]\" (data pin = \"judge2_origin\[3\]\", clock pin = \"button_judge\") is 11.164 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.650 ns + Longest pin register " "Info: + Longest pin to register delay is 14.650 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns judge2_origin\[3\] 1 PIN PIN_125 9 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_125; Fanout = 9; PIN Node = 'judge2_origin\[3\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "" { judge2_origin[3] } "NODE_NAME" } } { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.593 ns) + CELL(0.511 ns) 5.236 ns LessThan3~295 2 COMB LC_X7_Y7_N5 2 " "Info: 2: + IC(3.593 ns) + CELL(0.511 ns) = 5.236 ns; Loc. = LC_X7_Y7_N5; Fanout = 2; COMB Node = 'LessThan3~295'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "4.104 ns" { judge2_origin[3] LessThan3~295 } "NODE_NAME" } } { "e:/study/cpld1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/study/cpld1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.780 ns) + CELL(0.511 ns) 6.527 ns LessThan3~296 3 COMB LC_X7_Y7_N4 11 " "Info: 3: + IC(0.780 ns) + CELL(0.511 ns) = 6.527 ns; Loc. = LC_X7_Y7_N4; Fanout = 11; COMB Node = 'LessThan3~296'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "1.291 ns" { LessThan3~295 LessThan3~296 } "NODE_NAME" } } { "e:/study/cpld1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/study/cpld1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(0.511 ns) 8.938 ns t1\[0\]~2183 4 COMB LC_X10_Y7_N9 12 " "Info: 4: + IC(1.900 ns) + CELL(0.511 ns) = 8.938 ns; Loc. = LC_X10_Y7_N9; Fanout = 12; COMB Node = 't1\[0\]~2183'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "2.411 ns" { LessThan3~296 t1[0]~2183 } "NODE_NAME" } } { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.804 ns) + CELL(1.908 ns) 14.650 ns t1\[9\] 5 REG LC_X10_Y8_N5 1 " "Info: 5: + IC(3.804 ns) + CELL(1.908 ns) = 14.650 ns; Loc. = LC_X10_Y8_N5; Fanout = 1; REG Node = 't1\[9\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "5.712 ns" { t1[0]~2183 t1[9] } "NODE_NAME" } } { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.573 ns ( 31.22 % ) " "Info: Total cell delay = 4.573 ns ( 31.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.077 ns ( 68.78 % ) " "Info: Total interconnect delay = 10.077 ns ( 68.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "14.650 ns" { judge2_origin[3] LessThan3~295 LessThan3~296 t1[0]~2183 t1[9] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "14.650 ns" { judge2_origin[3] {} judge2_origin[3]~combout {} LessThan3~295 {} LessThan3~296 {} t1[0]~2183 {} t1[9] {} } { 0.000ns 0.000ns 3.593ns 0.780ns 1.900ns 3.804ns } { 0.000ns 1.132ns 0.511ns 0.511ns 0.511ns 1.908ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "button_judge destination 3.819 ns - Shortest register " "Info: - Shortest clock path from clock \"button_judge\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns button_judge 1 CLK PIN_18 42 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 42; CLK Node = 'button_judge'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "" { button_judge } "NODE_NAME" } } { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns t1\[9\] 2 REG LC_X10_Y8_N5 1 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X10_Y8_N5; Fanout = 1; REG Node = 't1\[9\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { button_judge t1[9] } "NODE_NAME" } } { "max_and_min.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/三位比较器/max_and_min.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { button_judge t1[9] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { button_judge {} button_judge~combout {} t1[9] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "14.650 ns" { judge2_origin[3] LessThan3~295 LessThan3~296 t1[0]~2183 t1[9] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "14.650 ns" { judge2_origin[3] {} judge2_origin[3]~combout {} LessThan3~295 {} LessThan3~296 {} t1[0]~2183 {} t1[9] {} } { 0.000ns 0.000ns 3.593ns 0.780ns 1.900ns 3.804ns } { 0.000ns 1.132ns 0.511ns 0.511ns 0.511ns 1.908ns } "" } } { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { button_judge t1[9] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { button_judge {} button_judge~combout {} t1[9] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}