compare.fit.qmsg

基于CPLD的签到器的设计

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "button_arrive Global clock in PIN 18 " "Info: Automatically promoted signal \"button_arrive\" to use Global clock in PIN 18" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 8 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "button_judge Global clock in PIN 20 " "Info: Automatically promoted signal \"button_judge\" to use Global clock in PIN 20" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 9 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "button_name Global clock in PIN 91 " "Info: Automatically promoted signal \"button_name\" to use Global clock in PIN 91" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 7 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "LessThan3~295 Global clock " "Info: Automatically promoted signal \"LessThan3~295\" to use Global clock" {  } { { "e:/study/cpld1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/study/cpld1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0}