compare.tan.qmsg

基于CPLD的签到器的设计

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "button_arrive register b1\[1\] register m\[2\]\[0\]\[3\] 37.03 MHz 27.002 ns Internal " "Info: Clock \"button_arrive\" has Internal fmax of 37.03 MHz between source register \"b1\[1\]\" and destination register \"m\[2\]\[0\]\[3\]\" (period= 27.002 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.792 ns + Longest register register " "Info: + Longest register to register delay is 12.792 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns b1\[1\] 1 REG LC_X5_Y7_N7 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y7_N7; Fanout = 11; REG Node = 'b1\[1\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "" { b1[1] } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.186 ns) + CELL(0.200 ns) 2.386 ns Mux15~293 2 COMB LC_X6_Y8_N1 6 " "Info: 2: + IC(2.186 ns) + CELL(0.200 ns) = 2.386 ns; Loc. = LC_X6_Y8_N1; Fanout = 6; COMB Node = 'Mux15~293'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "2.386 ns" { b1[1] Mux15~293 } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.239 ns) + CELL(0.914 ns) 4.539 ns Mux13~201 3 COMB LC_X7_Y8_N5 1 " "Info: 3: + IC(1.239 ns) + CELL(0.914 ns) = 4.539 ns; Loc. = LC_X7_Y8_N5; Fanout = 1; COMB Node = 'Mux13~201'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "2.153 ns" { Mux15~293 Mux13~201 } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.114 ns) + CELL(0.200 ns) 5.853 ns Mux13~202 4 COMB LC_X8_Y8_N6 1 " "Info: 4: + IC(1.114 ns) + CELL(0.200 ns) = 5.853 ns; Loc. = LC_X8_Y8_N6; Fanout = 1; COMB Node = 'Mux13~202'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "1.314 ns" { Mux13~201 Mux13~202 } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 6.358 ns Mux13~203 5 COMB LC_X8_Y8_N7 1 " "Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 6.358 ns; Loc. = LC_X8_Y8_N7; Fanout = 1; COMB Node = 'Mux13~203'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { Mux13~202 Mux13~203 } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 6.863 ns Mux13~204 6 COMB LC_X8_Y8_N8 3 " "Info: 6: + IC(0.305 ns) + CELL(0.200 ns) = 6.863 ns; Loc. = LC_X8_Y8_N8; Fanout = 3; COMB Node = 'Mux13~204'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { Mux13~203 Mux13~204 } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.203 ns) + CELL(0.511 ns) 8.577 ns Mux13~206 7 COMB LC_X9_Y8_N1 2 " "Info: 7: + IC(1.203 ns) + CELL(0.511 ns) = 8.577 ns; Loc. = LC_X9_Y8_N1; Fanout = 2; COMB Node = 'Mux13~206'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "1.714 ns" { Mux13~204 Mux13~206 } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.711 ns) + CELL(0.740 ns) 10.028 ns Add1~294 8 COMB LC_X9_Y8_N7 5 " "Info: 8: + IC(0.711 ns) + CELL(0.740 ns) = 10.028 ns; Loc. = LC_X9_Y8_N7; Fanout = 5; COMB Node = 'Add1~294'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "1.451 ns" { Mux13~206 Add1~294 } "NODE_NAME" } } { "e:/study/cpld1/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/study/cpld1/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.484 ns) + CELL(0.280 ns) 12.792 ns m\[2\]\[0\]\[3\] 9 REG LC_X10_Y8_N1 2 " "Info: 9: + IC(2.484 ns) + CELL(0.280 ns) = 12.792 ns; Loc. = LC_X10_Y8_N1; Fanout = 2; REG Node = 'm\[2\]\[0\]\[3\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "2.764 ns" { Add1~294 m[2][0][3] } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.245 ns ( 25.37 % ) " "Info: Total cell delay = 3.245 ns ( 25.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.547 ns ( 74.63 % ) " "Info: Total interconnect delay = 9.547 ns ( 74.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "12.792 ns" { b1[1] Mux15~293 Mux13~201 Mux13~202 Mux13~203 Mux13~204 Mux13~206 Add1~294 m[2][0][3] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "12.792 ns" { b1[1] {} Mux15~293 {} Mux13~201 {} Mux13~202 {} Mux13~203 {} Mux13~204 {} Mux13~206 {} Add1~294 {} m[2][0][3] {} } { 0.000ns 2.186ns 1.239ns 1.114ns 0.305ns 0.305ns 1.203ns 0.711ns 2.484ns } { 0.000ns 0.200ns 0.914ns 0.200ns 0.200ns 0.200ns 0.511ns 0.740ns 0.280ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "button_arrive destination 3.819 ns + Shortest register " "Info: + Shortest clock path from clock \"button_arrive\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns button_arrive 1 CLK PIN_18 26 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 26; CLK Node = 'button_arrive'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "" { button_arrive } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns m\[2\]\[0\]\[3\] 2 REG LC_X10_Y8_N1 2 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X10_Y8_N1; Fanout = 2; REG Node = 'm\[2\]\[0\]\[3\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { button_arrive m[2][0][3] } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { button_arrive m[2][0][3] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { button_arrive {} button_arrive~combout {} m[2][0][3] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "button_arrive source 3.819 ns - Longest register " "Info: - Longest clock path from clock \"button_arrive\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns button_arrive 1 CLK PIN_18 26 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 26; CLK Node = 'button_arrive'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "" { button_arrive } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns b1\[1\] 2 REG LC_X5_Y7_N7 11 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X5_Y7_N7; Fanout = 11; REG Node = 'b1\[1\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { button_arrive b1[1] } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { button_arrive b1[1] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { button_arrive {} button_arrive~combout {} b1[1] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { button_arrive m[2][0][3] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { button_arrive {} button_arrive~combout {} m[2][0][3] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { button_arrive b1[1] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { button_arrive {} button_arrive~combout {} b1[1] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 46 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 46 -1 0 } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 21 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "12.792 ns" { b1[1] Mux15~293 Mux13~201 Mux13~202 Mux13~203 Mux13~204 Mux13~206 Add1~294 m[2][0][3] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "12.792 ns" { b1[1] {} Mux15~293 {} Mux13~201 {} Mux13~202 {} Mux13~203 {} Mux13~204 {} Mux13~206 {} Add1~294 {} m[2][0][3] {} } { 0.000ns 2.186ns 1.239ns 1.114ns 0.305ns 0.305ns 1.203ns 0.711ns 2.484ns } { 0.000ns 0.200ns 0.914ns 0.200ns 0.200ns 0.200ns 0.511ns 0.740ns 0.280ns } "" } } { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { button_arrive m[2][0][3] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { button_arrive {} button_arrive~combout {} m[2][0][3] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { button_arrive b1[1] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { button_arrive {} button_arrive~combout {} b1[1] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "button_judge " "Info: No valid register-to-register data paths exist for clock \"button_judge\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "b1\[0\] clock_hour\[3\] button_arrive 4.450 ns register " "Info: tsu for register \"b1\[0\]\" (data pin = \"clock_hour\[3\]\", clock pin = \"button_arrive\") is 4.450 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.936 ns + Longest pin register " "Info: + Longest pin to register delay is 7.936 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clock_hour\[3\] 1 PIN PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_43; Fanout = 4; PIN Node = 'clock_hour\[3\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_hour[3] } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.421 ns) + CELL(0.740 ns) 5.293 ns process1~68 2 COMB LC_X5_Y7_N0 1 " "Info: 2: + IC(3.421 ns) + CELL(0.740 ns) = 5.293 ns; Loc. = LC_X5_Y7_N0; Fanout = 1; COMB Node = 'process1~68'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "4.161 ns" { clock_hour[3] process1~68 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.772 ns) + CELL(0.511 ns) 6.576 ns process1~69 3 COMB LC_X5_Y7_N8 2 " "Info: 3: + IC(0.772 ns) + CELL(0.511 ns) = 6.576 ns; Loc. = LC_X5_Y7_N8; Fanout = 2; COMB Node = 'process1~69'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "1.283 ns" { process1~68 process1~69 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.769 ns) + CELL(0.591 ns) 7.936 ns b1\[0\] 4 REG LC_X5_Y7_N3 11 " "Info: 4: + IC(0.769 ns) + CELL(0.591 ns) = 7.936 ns; Loc. = LC_X5_Y7_N3; Fanout = 11; REG Node = 'b1\[0\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "1.360 ns" { process1~69 b1[0] } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.974 ns ( 37.47 % ) " "Info: Total cell delay = 2.974 ns ( 37.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.962 ns ( 62.53 % ) " "Info: Total interconnect delay = 4.962 ns ( 62.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "7.936 ns" { clock_hour[3] process1~68 process1~69 b1[0] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "7.936 ns" { clock_hour[3] {} clock_hour[3]~combout {} process1~68 {} process1~69 {} b1[0] {} } { 0.000ns 0.000ns 3.421ns 0.772ns 0.769ns } { 0.000ns 1.132ns 0.740ns 0.511ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 46 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "button_arrive destination 3.819 ns - Shortest register " "Info: - Shortest clock path from clock \"button_arrive\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns button_arrive 1 CLK PIN_18 26 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 26; CLK Node = 'button_arrive'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "" { button_arrive } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns b1\[0\] 2 REG LC_X5_Y7_N3 11 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X5_Y7_N3; Fanout = 11; REG Node = 'b1\[0\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { button_arrive b1[0] } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { button_arrive b1[0] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { button_arrive {} button_arrive~combout {} b1[0] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "7.936 ns" { clock_hour[3] process1~68 process1~69 b1[0] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "7.936 ns" { clock_hour[3] {} clock_hour[3]~combout {} process1~68 {} process1~69 {} b1[0] {} } { 0.000ns 0.000ns 3.421ns 0.772ns 0.769ns } { 0.000ns 1.132ns 0.740ns 0.511ns 0.591ns } "" } } { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { button_arrive b1[0] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { button_arrive {} button_arrive~combout {} b1[0] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "button_arrive b_out\[1\] b1\[1\] 10.385 ns register " "Info: tco from clock \"button_arrive\" to destination pin \"b_out\[1\]\" through register \"b1\[1\]\" is 10.385 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "button_arrive source 3.819 ns + Longest register " "Info: + Longest clock path from clock \"button_arrive\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns button_arrive 1 CLK PIN_18 26 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 26; CLK Node = 'button_arrive'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "" { button_arrive } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns b1\[1\] 2 REG LC_X5_Y7_N7 11 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X5_Y7_N7; Fanout = 11; REG Node = 'b1\[1\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { button_arrive b1[1] } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { button_arrive b1[1] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { button_arrive {} button_arrive~combout {} b1[1] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 46 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.190 ns + Longest register pin " "Info: + Longest register to pin delay is 6.190 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns b1\[1\] 1 REG LC_X5_Y7_N7 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y7_N7; Fanout = 11; REG Node = 'b1\[1\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "" { b1[1] } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.868 ns) + CELL(2.322 ns) 6.190 ns b_out\[1\] 2 PIN PIN_131 0 " "Info: 2: + IC(3.868 ns) + CELL(2.322 ns) = 6.190 ns; Loc. = PIN_131; Fanout = 0; PIN Node = 'b_out\[1\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "6.190 ns" { b1[1] b_out[1] } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 37.51 % ) " "Info: Total cell delay = 2.322 ns ( 37.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.868 ns ( 62.49 % ) " "Info: Total interconnect delay = 3.868 ns ( 62.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "6.190 ns" { b1[1] b_out[1] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "6.190 ns" { b1[1] {} b_out[1] {} } { 0.000ns 3.868ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { button_arrive b1[1] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { button_arrive {} button_arrive~combout {} b1[1] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "6.190 ns" { b1[1] b_out[1] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "6.190 ns" { b1[1] {} b_out[1] {} } { 0.000ns 3.868ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}