compare.tan.qmsg

基于CPLD的签到器的设计

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "ITDB_FOUND_DFFEA_LATCHES" "" "Info: Timing Analysis found one or more latches implemented as registers" { { "Info" "ITDB_DFFEA_LATCH_NODE" "m\[0\]\[2\]\[1\] " "Info: Register m\[0\]\[2\]\[1\] is a latch" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 64 -1 0 } }  } 0 0 "Register %1!s! is a latch" 0 0 "" 0} { "Info" "ITDB_DFFEA_LATCH_NODE" "m\[0\]\[2\]\[0\] " "Info: Register m\[0\]\[2\]\[0\] is a latch" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 64 -1 0 } }  } 0 0 "Register %1!s! is a latch" 0 0 "" 0} { "Info" "ITDB_DFFEA_LATCH_NODE" "m\[0\]\[2\]\[2\] " "Info: Register m\[0\]\[2\]\[2\] is a latch" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 64 -1 0 } }  } 0 0 "Register %1!s! is a latch" 0 0 "" 0} { "Info" "ITDB_DFFEA_LATCH_NODE" "m\[0\]\[2\]\[3\] " "Info: Register m\[0\]\[2\]\[3\] is a latch" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 64 -1 0 } }  } 0 0 "Register %1!s! is a latch" 0 0 "" 0} { "Info" "ITDB_DFFEA_LATCH_NODE" "m\[1\]\[2\]\[1\] " "Info: Register m\[1\]\[2\]\[1\] is a latch" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 64 -1 0 } }  } 0 0 "Register %1!s! is a latch" 0 0 "" 0} { "Info" "ITDB_DFFEA_LATCH_NODE" "m\[1\]\[2\]\[0\] " "Info: Register m\[1\]\[2\]\[0\] is a latch" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 64 -1 0 } }  } 0 0 "Register %1!s! is a latch" 0 0 "" 0} { "Info" "ITDB_DFFEA_LATCH_NODE" "m\[1\]\[2\]\[2\] " "Info: Register m\[1\]\[2\]\[2\] is a latch" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 64 -1 0 } }  } 0 0 "Register %1!s! is a latch" 0 0 "" 0} { "Info" "ITDB_DFFEA_LATCH_NODE" "m\[1\]\[2\]\[3\] " "Info: Register m\[1\]\[2\]\[3\] is a latch" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 64 -1 0 } }  } 0 0 "Register %1!s! is a latch" 0 0 "" 0} { "Info" "ITDB_DFFEA_LATCH_NODE" "m\[2\]\[2\]\[1\] " "Info: Register m\[2\]\[2\]\[1\] is a latch" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 64 -1 0 } }  } 0 0 "Register %1!s! is a latch" 0 0 "" 0} { "Info" "ITDB_DFFEA_LATCH_NODE" "m\[2\]\[2\]\[0\] " "Info: Register m\[2\]\[2\]\[0\] is a latch" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 64 -1 0 } }  } 0 0 "Register %1!s! is a latch" 0 0 "" 0} { "Info" "ITDB_DFFEA_LATCH_NODE" "m\[2\]\[2\]\[2\] " "Info: Register m\[2\]\[2\]\[2\] is a latch" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 64 -1 0 } }  } 0 0 "Register %1!s! is a latch" 0 0 "" 0} { "Info" "ITDB_DFFEA_LATCH_NODE" "m\[2\]\[2\]\[3\] " "Info: Register m\[2\]\[2\]\[3\] is a latch" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 64 -1 0 } }  } 0 0 "Register %1!s! is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis found one or more latches implemented as registers" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "button_name " "Info: Assuming node \"button_name\" is an undefined clock" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 7 -1 0 } } { "e:/study/cpld1/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/study/cpld1/quartus/bin/Assignment Editor.qase" 1 { { 0 "button_name" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "button_arrive " "Info: Assuming node \"button_arrive\" is an undefined clock" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 8 -1 0 } } { "e:/study/cpld1/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/study/cpld1/quartus/bin/Assignment Editor.qase" 1 { { 0 "button_arrive" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "button_judge " "Info: Assuming node \"button_judge\" is an undefined clock" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 9 -1 0 } } { "e:/study/cpld1/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/study/cpld1/quartus/bin/Assignment Editor.qase" 1 { { 0 "button_judge" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "button_name register register a1\[1\] a1\[1\] 304.04 MHz Internal " "Info: Clock \"button_name\" Internal fmax is restricted to 304.04 MHz between source register \"a1\[1\]\" and destination register \"a1\[1\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 3.289 ns " "Info: fmax restricted to clock pin edge rate 3.289 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.024 ns + Longest register register " "Info: + Longest register to register delay is 2.024 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns a1\[1\] 1 REG LC_X10_Y8_N2 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y8_N2; Fanout = 15; REG Node = 'a1\[1\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "" { a1[1] } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.963 ns) + CELL(1.061 ns) 2.024 ns a1\[1\] 2 REG LC_X10_Y8_N2 15 " "Info: 2: + IC(0.963 ns) + CELL(1.061 ns) = 2.024 ns; Loc. = LC_X10_Y8_N2; Fanout = 15; REG Node = 'a1\[1\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "2.024 ns" { a1[1] a1[1] } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.061 ns ( 52.42 % ) " "Info: Total cell delay = 1.061 ns ( 52.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.963 ns ( 47.58 % ) " "Info: Total interconnect delay = 0.963 ns ( 47.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "2.024 ns" { a1[1] a1[1] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "2.024 ns" { a1[1] {} a1[1] {} } { 0.000ns 0.963ns } { 0.000ns 1.061ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "button_name destination 3.699 ns + Shortest register " "Info: + Shortest clock path from clock \"button_name\" to destination register is 3.699 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns button_name 1 CLK PIN_91 2 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_91; Fanout = 2; CLK Node = 'button_name'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "" { button_name } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.618 ns) + CELL(0.918 ns) 3.699 ns a1\[1\] 2 REG LC_X10_Y8_N2 15 " "Info: 2: + IC(1.618 ns) + CELL(0.918 ns) = 3.699 ns; Loc. = LC_X10_Y8_N2; Fanout = 15; REG Node = 'a1\[1\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "2.536 ns" { button_name a1[1] } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.26 % ) " "Info: Total cell delay = 2.081 ns ( 56.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.618 ns ( 43.74 % ) " "Info: Total interconnect delay = 1.618 ns ( 43.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.699 ns" { button_name a1[1] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.699 ns" { button_name {} button_name~combout {} a1[1] {} } { 0.000ns 0.000ns 1.618ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "button_name source 3.699 ns - Longest register " "Info: - Longest clock path from clock \"button_name\" to source register is 3.699 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns button_name 1 CLK PIN_91 2 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_91; Fanout = 2; CLK Node = 'button_name'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "" { button_name } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.618 ns) + CELL(0.918 ns) 3.699 ns a1\[1\] 2 REG LC_X10_Y8_N2 15 " "Info: 2: + IC(1.618 ns) + CELL(0.918 ns) = 3.699 ns; Loc. = LC_X10_Y8_N2; Fanout = 15; REG Node = 'a1\[1\]'" {  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "2.536 ns" { button_name a1[1] } "NODE_NAME" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.26 % ) " "Info: Total cell delay = 2.081 ns ( 56.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.618 ns ( 43.74 % ) " "Info: Total interconnect delay = 1.618 ns ( 43.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.699 ns" { button_name a1[1] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.699 ns" { button_name {} button_name~combout {} a1[1] {} } { 0.000ns 0.000ns 1.618ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.699 ns" { button_name a1[1] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.699 ns" { button_name {} button_name~combout {} a1[1] {} } { 0.000ns 0.000ns 1.618ns } { 0.000ns 1.163ns 0.918ns } "" } } { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.699 ns" { button_name a1[1] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.699 ns" { button_name {} button_name~combout {} a1[1] {} } { 0.000ns 0.000ns 1.618ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "2.024 ns" { a1[1] a1[1] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "2.024 ns" { a1[1] {} a1[1] {} } { 0.000ns 0.963ns } { 0.000ns 1.061ns } "" } } { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.699 ns" { button_name a1[1] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.699 ns" { button_name {} button_name~combout {} a1[1] {} } { 0.000ns 0.000ns 1.618ns } { 0.000ns 1.163ns 0.918ns } "" } } { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "3.699 ns" { button_name a1[1] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "3.699 ns" { button_name {} button_name~combout {} a1[1] {} } { 0.000ns 0.000ns 1.618ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/study/cpld1/quartus/bin/TimingClosureFloorplan.fld" "" "" { a1[1] } "NODE_NAME" } } { "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/study/cpld1/quartus/bin/Technology_Viewer.qrui" "" { a1[1] {} } {  } {  } "" } } { "compare.vhd" "" { Text "E:/study/CPLD/竞赛用签到器/数据处理模块/实时比较（7 days later judge）/compare.vhd" 32 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}