prev_cmp_music_chooser.fit.qmsg

基于CPLD的签到器的设计

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "11.222 ns pin pin " "Info: Estimated most critical path is pin to pin delay of 11.222 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns min2\[2\] 1 PIN PIN_44 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_44; Fanout = 1; PIN Node = 'min2\[2\]'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { min2[2] } "NODE_NAME" } } { "music_chooser.vhd" "" { Text "E:/VHDL/music_chooser/music_chooser.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.374 ns) + CELL(0.200 ns) 3.706 ns process0~134 2 COMB LAB_X4_Y7 1 " "Info: 2: + IC(2.374 ns) + CELL(0.200 ns) = 3.706 ns; Loc. = LAB_X4_Y7; Fanout = 1; COMB Node = 'process0~134'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "2.574 ns" { min2[2] process0~134 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.672 ns) + CELL(0.511 ns) 4.889 ns process0~135 3 COMB LAB_X4_Y7 2 " "Info: 3: + IC(0.672 ns) + CELL(0.511 ns) = 4.889 ns; Loc. = LAB_X4_Y7; Fanout = 2; COMB Node = 'process0~135'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "1.183 ns" { process0~134 process0~135 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.269 ns) + CELL(0.914 ns) 6.072 ns process0~0 4 COMB LAB_X4_Y7 1 " "Info: 4: + IC(0.269 ns) + CELL(0.914 ns) = 6.072 ns; Loc. = LAB_X4_Y7; Fanout = 1; COMB Node = 'process0~0'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "1.183 ns" { process0~135 process0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.672 ns) + CELL(0.511 ns) 7.255 ns model2~286 5 COMB LAB_X4_Y7 1 " "Info: 5: + IC(0.672 ns) + CELL(0.511 ns) = 7.255 ns; Loc. = LAB_X4_Y7; Fanout = 1; COMB Node = 'model2~286'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "1.183 ns" { process0~0 model2~286 } "NODE_NAME" } } { "music_chooser.vhd" "" { Text "E:/VHDL/music_chooser/music_chooser.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.645 ns) + CELL(2.322 ns) 11.222 ns what2\[0\] 6 PIN PIN_14 0 " "Info: 6: + IC(1.645 ns) + CELL(2.322 ns) = 11.222 ns; Loc. = PIN_14; Fanout = 0; PIN Node = 'what2\[0\]'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "3.967 ns" { model2~286 what2[0] } "NODE_NAME" } } { "music_chooser.vhd" "" { Text "E:/VHDL/music_chooser/music_chooser.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.590 ns ( 49.81 % ) " "Info: Total cell delay = 5.590 ns ( 49.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.632 ns ( 50.19 % ) " "Info: Total interconnect delay = 5.632 ns ( 50.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "11.222 ns" { min2[2] process0~134 process0~135 process0~0 model2~286 what2[0] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X0_Y0 X8_Y11 " "Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X0_Y0 to location X8_Y11" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/VHDL/music_chooser/music_chooser.fit.smsg " "Info: Generated suppressed messages file E:/VHDL/music_chooser/music_chooser.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "167 " "Info: Allocated 167 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 29 01:16:41 2008 " "Info: Processing ended: Tue Jul 29 01:16:41 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}