prev_cmp_clock.qmsg

来自「基于CPLD的签到器的设计」· QMSG 代码 · 共 52 行 · 第 1/3 页

{ "Info" "ISGN_MEGAFN_DESCENDANT" "day:u7\|lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:result_node day:u7\|lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"day:u7\|lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"day:u7\|lpm_add_sub:Add1\"" {  } { { "addcore.tdf" "" { Text "e:/program files/quartus72/quartus/libraries/megafunctions/addcore.tdf" 123 6 0 } } { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "day:u7\|lpm_add_sub:Add1 " "Info: Instantiated megafunction \"day:u7\|lpm_add_sub:Add1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 5 " "Info: Parameter \"LPM_WIDTH\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "day:u7\|lpm_add_sub:Add1\|altshift:result_ext_latency_ffs day:u7\|lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"day:u7\|lpm_add_sub:Add1\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"day:u7\|lpm_add_sub:Add1\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/program files/quartus72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } } { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "day:u7\|lpm_add_sub:Add1 " "Info: Instantiated megafunction \"day:u7\|lpm_add_sub:Add1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 5 " "Info: Parameter \"LPM_WIDTH\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "hour:u6\|lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"hour:u6\|lpm_add_sub:Add1\"" {  } { { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "divide_clock:u0\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"divide_clock:u0\|lpm_add_sub:Add0\"" {  } { { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "divide_clock:u0\|lpm_add_sub:Add0\|addcore:adder divide_clock:u0\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"divide_clock:u0\|lpm_add_sub:Add0\|addcore:adder\", which is child of megafunction instantiation \"divide_clock:u0\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/program files/quartus72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "divide_clock:u0\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"divide_clock:u0\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 25 " "Info: Parameter \"LPM_WIDTH\" = \"25\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "divide_clock:u0\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node divide_clock:u0\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"divide_clock:u0\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"divide_clock:u0\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "e:/program files/quartus72/quartus/libraries/megafunctions/addcore.tdf" 97 2 0 } } { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "divide_clock:u0\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"divide_clock:u0\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 25 " "Info: Parameter \"LPM_WIDTH\" = \"25\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "divide_clock:u0\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node divide_clock:u0\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"divide_clock:u0\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"divide_clock:u0\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "e:/program files/quartus72/quartus/libraries/megafunctions/addcore.tdf" 123 6 0 } } { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "divide_clock:u0\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"divide_clock:u0\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 25 " "Info: Parameter \"LPM_WIDTH\" = \"25\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "divide_clock:u0\|lpm_add_sub:Add0\|altshift:result_ext_latency_ffs divide_clock:u0\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"divide_clock:u0\|lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"divide_clock:u0\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/program files/quartus72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } } { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "divide_clock:u0\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"divide_clock:u0\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 25 " "Info: Parameter \"LPM_WIDTH\" = \"25\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 0 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "159 " "Info: Allocated 159 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 30 19:49:33 2008 " "Info: Processing ended: Wed Jul 30 19:49:33 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}