prev_cmp_clock.qmsg

基于CPLD的签到器的设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 30 19:49:30 2008 " "Info: Processing started: Wed Jul 30 19:49:30 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "day.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file day.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 day-d3 " "Info: Found design unit 1: day-d3" {  } { { "day.vhd" "" { Text "E:/闹钟模块/签到器clock/day.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 day " "Info: Found entity 1: day" {  } { { "day.vhd" "" { Text "E:/闹钟模块/签到器clock/day.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "count.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file count.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 count-c2 " "Info: Found design unit 1: count-c2" {  } { { "count.vhd" "" { Text "E:/闹钟模块/签到器clock/count.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 count " "Info: Found entity 1: count" {  } { { "count.vhd" "" { Text "E:/闹钟模块/签到器clock/count.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock-art " "Info: Found design unit 1: clock-art" {  } { { "clock.vhd" "" { Text "E:/闹钟模块/签到器clock/clock.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.vhd" "" { Text "E:/闹钟模块/签到器clock/clock.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "divide_clock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file divide_clock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divide_clock-a " "Info: Found design unit 1: divide_clock-a" {  } { { "divide_clock.vhd" "" { Text "E:/闹钟模块/签到器clock/divide_clock.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 divide_clock " "Info: Found entity 1: divide_clock" {  } { { "divide_clock.vhd" "" { Text "E:/闹钟模块/签到器clock/divide_clock.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hour.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file hour.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 hour-h3 " "Info: Found design unit 1: hour-h3" {  } { { "hour.vhd" "" { Text "E:/闹钟模块/签到器clock/hour.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 hour " "Info: Found entity 1: hour" {  } { { "hour.vhd" "" { Text "E:/闹钟模块/签到器clock/hour.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "xuanze.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file xuanze.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 xuanze-art " "Info: Found design unit 1: xuanze-art" {  } { { "xuanze.vhd" "" { Text "E:/闹钟模块/签到器clock/xuanze.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 xuanze " "Info: Found entity 1: xuanze" {  } { { "xuanze.vhd" "" { Text "E:/闹钟模块/签到器clock/xuanze.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock " "Info: Elaborating entity \"clock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "divide_clock divide_clock:u0 " "Info: Elaborating entity \"divide_clock\" for hierarchy \"divide_clock:u0\"" {  } { { "clock.vhd" "u0" { Text "E:/闹钟模块/签到器clock/clock.vhd" 57 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "count count:u2 " "Info: Elaborating entity \"count\" for hierarchy \"count:u2\"" {  } { { "clock.vhd" "u2" { Text "E:/闹钟模块/签到器clock/clock.vhd" 58 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "xuanze xuanze:u3 " "Info: Elaborating entity \"xuanze\" for hierarchy \"xuanze:u3\"" {  } { { "clock.vhd" "u3" { Text "E:/闹钟模块/签到器clock/clock.vhd" 59 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hour hour:u6 " "Info: Elaborating entity \"hour\" for hierarchy \"hour:u6\"" {  } { { "clock.vhd" "u6" { Text "E:/闹钟模块/签到器clock/clock.vhd" 62 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "day day:u7 " "Info: Elaborating entity \"day\" for hierarchy \"day:u7\"" {  } { { "clock.vhd" "u7" { Text "E:/闹钟模块/签到器clock/clock.vhd" 63 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "12 " "Info: Inferred 12 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "day:u7\|Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"day:u7\|Add0\"" {  } { { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add0" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "day:u7\|Add1 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"day:u7\|Add1\"" {  } { { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "Add1" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "hour:u6\|Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"hour:u6\|Add0\"" {  } { { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add0" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "hour:u6\|Add1 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"hour:u6\|Add1\"" {  } { { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "Add1" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "hour:u6\|Add2 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"hour:u6\|Add2\"" {  } { { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add2" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "count:u4\|Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"count:u4\|Add0\"" {  } { { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add0" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "count:u4\|Add1 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"count:u4\|Add1\"" {  } { { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "Add1" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "count:u4\|Add2 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"count:u4\|Add2\"" {  } { { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add2" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "count:u2\|Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"count:u2\|Add0\"" {  } { { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add0" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "count:u2\|Add1 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"count:u2\|Add1\"" {  } { { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "Add1" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "count:u2\|Add2 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"count:u2\|Add2\"" {  } { { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add2" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "divide_clock:u0\|Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"divide_clock:u0\|Add0\"" {  } { { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add0" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../program files/quartus72/quartus/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../program files/quartus72/quartus/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "e:/program files/quartus72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 102 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "day:u7\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"day:u7\|lpm_add_sub:Add0\"" {  } { { "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/program files/quartus72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}