📄 clock.sim.vwf

📁 基于CPLD的签到器的设计
💻 VWF
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		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 102400.0;
			LEVEL 0 FOR 102400.0;
		}
		LEVEL 1 FOR 102400.0;
		LEVEL 0 FOR 112640.0;
		LEVEL 1 FOR 28810.0;
	}
}

TRANSITION_LIST("clock_second[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 76790.0;
		NODE
		{
			REPEAT = 2;
			NODE
			{
				REPEAT = 5;
				LEVEL 1 FOR 20480.0;
				LEVEL 0 FOR 81920.0;
			}
			LEVEL 1 FOR 20480.0;
			LEVEL 0 FOR 92160.0;
		}
		NODE
		{
			REPEAT = 5;
			LEVEL 1 FOR 20480.0;
			LEVEL 0 FOR 81920.0;
		}
		LEVEL 1 FOR 20480.0;
		LEVEL 0 FOR 92160.0;
		LEVEL 1 FOR 20480.0;
		LEVEL 0 FOR 28810.0;
	}
}

TRANSITION_LIST("clock_second[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 35830.0;
		NODE
		{
			REPEAT = 2;
			NODE
			{
				REPEAT = 5;
				LEVEL 1 FOR 40960.0;
				LEVEL 0 FOR 61440.0;
			}
			LEVEL 1 FOR 40960.0;
			LEVEL 0 FOR 71680.0;
		}
		NODE
		{
			REPEAT = 5;
			LEVEL 1 FOR 40960.0;
			LEVEL 0 FOR 61440.0;
		}
		LEVEL 1 FOR 40960.0;
		LEVEL 0 FOR 71680.0;
		LEVEL 1 FOR 40960.0;
		LEVEL 0 FOR 49290.0;
	}
}

TRANSITION_LIST("clock_second[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 15350.0;
		NODE
		{
			REPEAT = 2;
			NODE
			{
				REPEAT = 5;
				LEVEL 1 FOR 20480.0;
				LEVEL 0 FOR 20480.0;
				LEVEL 1 FOR 20480.0;
				LEVEL 0 FOR 40960.0;
			}
			LEVEL 1 FOR 20480.0;
			LEVEL 0 FOR 20480.0;
			LEVEL 1 FOR 20480.0;
			LEVEL 0 FOR 51200.0;
		}
		NODE
		{
			REPEAT = 5;
			LEVEL 1 FOR 20480.0;
			LEVEL 0 FOR 20480.0;
			LEVEL 1 FOR 20480.0;
			LEVEL 0 FOR 40960.0;
		}
		LEVEL 1 FOR 20480.0;
		LEVEL 0 FOR 20480.0;
		LEVEL 1 FOR 20480.0;
		LEVEL 0 FOR 51200.0;
		LEVEL 1 FOR 20480.0;
		LEVEL 0 FOR 20480.0;
		LEVEL 1 FOR 20480.0;
		LEVEL 0 FOR 40960.0;
		LEVEL 1 FOR 8330.0;
	}
}

TRANSITION_LIST("clock_second[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5110.0;
		NODE
		{
			REPEAT = 2;
			NODE
			{
				REPEAT = 29;
				LEVEL 1 FOR 10240.0;
				LEVEL 0 FOR 10240.0;
			}
			LEVEL 1 FOR 10240.0;
			LEVEL 0 FOR 20480.0;
		}
		NODE
		{
			REPEAT = 29;
			LEVEL 1 FOR 10240.0;
			LEVEL 0 FOR 10240.0;
		}
		LEVEL 1 FOR 10240.0;
		LEVEL 0 FOR 20480.0;
		NODE
		{
			REPEAT = 5;
			LEVEL 1 FOR 10240.0;
			LEVEL 0 FOR 10240.0;
		}
		LEVEL 1 FOR 10240.0;
		LEVEL 0 FOR 8330.0;
	}
}

TRANSITION_LIST("clock_minute[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2000000.0;
	}
}

TRANSITION_LIST("clock_minute[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2000000.0;
	}
}

TRANSITION_LIST("clock_minute[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2000000.0;
	}
}

TRANSITION_LIST("clock_minute[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2000000.0;
	}
}

TRANSITION_LIST("clock_minute[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2000000.0;
	}
}

TRANSITION_LIST("clock_minute[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2000000.0;
	}
}

TRANSITION_LIST("clock_minute[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1244150.0;
		LEVEL 1 FOR 755850.0;
	}
}

TRANSITION_LIST("clock_minute[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 619510.0;
		LEVEL 1 FOR 624640.0;
		LEVEL 0 FOR 624640.0;
		LEVEL 1 FOR 131210.0;
	}
}

DISPLAY_LINE
{
	CHANNEL = "clock_666M";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clock_day";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clock_k0";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 2;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clock_k1";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 3;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clock_reset";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 4;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clock_second";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 5;
	TREE_LEVEL = 0;
	CHILDREN = 6, 7, 8, 9, 10, 11, 12, 13;
}

DISPLAY_LINE
{
	CHANNEL = "clock_second[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 6;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "clock_second[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 7;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "clock_second[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 8;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "clock_second[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 9;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "clock_second[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 10;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "clock_second[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 11;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "clock_second[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 12;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "clock_second[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 13;
	TREE_LEVEL = 1;
	PARENT = 5;
}

DISPLAY_LINE
{
	CHANNEL = "clock_minute";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 14;
	TREE_LEVEL = 0;
	CHILDREN = 15, 16, 17, 18, 19, 20, 21, 22;
}

DISPLAY_LINE
{
	CHANNEL = "clock_minute[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 15;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "clock_minute[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 16;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "clock_minute[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 17;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "clock_minute[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 18;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "clock_minute[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 19;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "clock_minute[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 20;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "clock_minute[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 21;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "clock_minute[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 22;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "clock_hour";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 23;
	TREE_LEVEL = 0;
	CHILDREN = 24, 25, 26, 27, 28, 29, 30, 31;
}

DISPLAY_LINE
{
	CHANNEL = "clock_hour[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 24;
	TREE_LEVEL = 1;
	PARENT = 23;
}

DISPLAY_LINE
{
	CHANNEL = "clock_hour[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 25;
	TREE_LEVEL = 1;
	PARENT = 23;
}

DISPLAY_LINE
{
	CHANNEL = "clock_hour[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 26;
	TREE_LEVEL = 1;
	PARENT = 23;
}

DISPLAY_LINE
{
	CHANNEL = "clock_hour[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 27;
	TREE_LEVEL = 1;
	PARENT = 23;
}

DISPLAY_LINE
{
	CHANNEL = "clock_hour[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 28;
	TREE_LEVEL = 1;
	PARENT = 23;
}

DISPLAY_LINE
{
	CHANNEL = "clock_hour[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 29;
	TREE_LEVEL = 1;
	PARENT = 23;
}

DISPLAY_LINE
{
	CHANNEL = "clock_hour[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 30;
	TREE_LEVEL = 1;
	PARENT = 23;
}

DISPLAY_LINE
{
	CHANNEL = "clock_hour[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 31;
	TREE_LEVEL = 1;
	PARENT = 23;
}

TIME_BAR
{
	TIME = 9000;
	MASTER = TRUE;
}
;
上一页 12
💿 文件大小 5389 K
👤 上传用户 hqbbsw
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

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