prev_cmp_clock.tan.qmsg

基于CPLD的签到器的设计

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock_k1 register hour:u6\|data\[0\] register hour:u6\|data\[2\] 159.39 MHz 6.274 ns Internal " "Info: Clock \"clock_k1\" has Internal fmax of 159.39 MHz between source register \"hour:u6\|data\[0\]\" and destination register \"hour:u6\|data\[2\]\" (period= 6.274 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.565 ns + Longest register register " "Info: + Longest register to register delay is 5.565 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns hour:u6\|data\[0\] 1 REG LC_X10_Y9_N7 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y9_N7; Fanout = 9; REG Node = 'hour:u6\|data\[0\]'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { hour:u6|data[0] } "NODE_NAME" } } { "hour.vhd" "" { Text "E:/闹钟模块/签到器clock/hour.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.347 ns) + CELL(0.914 ns) 2.261 ns hour:u6\|process0~53 2 COMB LC_X10_Y9_N4 1 " "Info: 2: + IC(1.347 ns) + CELL(0.914 ns) = 2.261 ns; Loc. = LC_X10_Y9_N4; Fanout = 1; COMB Node = 'hour:u6\|process0~53'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "2.261 ns" { hour:u6|data[0] hour:u6|process0~53 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.794 ns) + CELL(0.511 ns) 3.566 ns hour:u6\|process0~55 3 COMB LC_X10_Y9_N1 8 " "Info: 3: + IC(0.794 ns) + CELL(0.511 ns) = 3.566 ns; Loc. = LC_X10_Y9_N1; Fanout = 8; COMB Node = 'hour:u6\|process0~55'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "1.305 ns" { hour:u6|process0~53 hour:u6|process0~55 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.195 ns) + CELL(0.804 ns) 5.565 ns hour:u6\|data\[2\] 4 REG LC_X10_Y9_N2 5 " "Info: 4: + IC(1.195 ns) + CELL(0.804 ns) = 5.565 ns; Loc. = LC_X10_Y9_N2; Fanout = 5; REG Node = 'hour:u6\|data\[2\]'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "1.999 ns" { hour:u6|process0~55 hour:u6|data[2] } "NODE_NAME" } } { "hour.vhd" "" { Text "E:/闹钟模块/签到器clock/hour.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.229 ns ( 40.05 % ) " "Info: Total cell delay = 2.229 ns ( 40.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.336 ns ( 59.95 % ) " "Info: Total interconnect delay = 3.336 ns ( 59.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "5.565 ns" { hour:u6|data[0] hour:u6|process0~53 hour:u6|process0~55 hour:u6|data[2] } "NODE_NAME" } } { "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "5.565 ns" { hour:u6|data[0] {} hour:u6|process0~53 {} hour:u6|process0~55 {} hour:u6|data[2] {} } { 0.000ns 1.347ns 0.794ns 1.195ns } { 0.000ns 0.914ns 0.511ns 0.804ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_k1 destination 9.678 ns + Shortest register " "Info: + Shortest clock path from clock \"clock_k1\" to destination register is 9.678 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clock_k1 1 CLK PIN_66 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_66; Fanout = 1; CLK Node = 'clock_k1'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_k1 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/闹钟模块/签到器clock/clock.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.025 ns) + CELL(0.740 ns) 4.897 ns xuanze:u5\|b 2 COMB LC_X11_Y7_N5 9 " "Info: 2: + IC(3.025 ns) + CELL(0.740 ns) = 4.897 ns; Loc. = LC_X11_Y7_N5; Fanout = 9; COMB Node = 'xuanze:u5\|b'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "3.765 ns" { clock_k1 xuanze:u5|b } "NODE_NAME" } } { "xuanze.vhd" "" { Text "E:/闹钟模块/签到器clock/xuanze.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.863 ns) + CELL(0.918 ns) 9.678 ns hour:u6\|data\[2\] 3 REG LC_X10_Y9_N2 5 " "Info: 3: + IC(3.863 ns) + CELL(0.918 ns) = 9.678 ns; Loc. = LC_X10_Y9_N2; Fanout = 5; REG Node = 'hour:u6\|data\[2\]'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "4.781 ns" { xuanze:u5|b hour:u6|data[2] } "NODE_NAME" } } { "hour.vhd" "" { Text "E:/闹钟模块/签到器clock/hour.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.790 ns ( 28.83 % ) " "Info: Total cell delay = 2.790 ns ( 28.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.888 ns ( 71.17 % ) " "Info: Total interconnect delay = 6.888 ns ( 71.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "9.678 ns" { clock_k1 xuanze:u5|b hour:u6|data[2] } "NODE_NAME" } } { "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "9.678 ns" { clock_k1 {} clock_k1~combout {} xuanze:u5|b {} hour:u6|data[2] {} } { 0.000ns 0.000ns 3.025ns 3.863ns } { 0.000ns 1.132ns 0.740ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_k1 source 9.678 ns - Longest register " "Info: - Longest clock path from clock \"clock_k1\" to source register is 9.678 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clock_k1 1 CLK PIN_66 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_66; Fanout = 1; CLK Node = 'clock_k1'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_k1 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/闹钟模块/签到器clock/clock.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.025 ns) + CELL(0.740 ns) 4.897 ns xuanze:u5\|b 2 COMB LC_X11_Y7_N5 9 " "Info: 2: + IC(3.025 ns) + CELL(0.740 ns) = 4.897 ns; Loc. = LC_X11_Y7_N5; Fanout = 9; COMB Node = 'xuanze:u5\|b'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "3.765 ns" { clock_k1 xuanze:u5|b } "NODE_NAME" } } { "xuanze.vhd" "" { Text "E:/闹钟模块/签到器clock/xuanze.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.863 ns) + CELL(0.918 ns) 9.678 ns hour:u6\|data\[0\] 3 REG LC_X10_Y9_N7 9 " "Info: 3: + IC(3.863 ns) + CELL(0.918 ns) = 9.678 ns; Loc. = LC_X10_Y9_N7; Fanout = 9; REG Node = 'hour:u6\|data\[0\]'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "4.781 ns" { xuanze:u5|b hour:u6|data[0] } "NODE_NAME" } } { "hour.vhd" "" { Text "E:/闹钟模块/签到器clock/hour.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.790 ns ( 28.83 % ) " "Info: Total cell delay = 2.790 ns ( 28.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.888 ns ( 71.17 % ) " "Info: Total interconnect delay = 6.888 ns ( 71.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "9.678 ns" { clock_k1 xuanze:u5|b hour:u6|data[0] } "NODE_NAME" } } { "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "9.678 ns" { clock_k1 {} clock_k1~combout {} xuanze:u5|b {} hour:u6|data[0] {} } { 0.000ns 0.000ns 3.025ns 3.863ns } { 0.000ns 1.132ns 0.740ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "9.678 ns" { clock_k1 xuanze:u5|b hour:u6|data[2] } "NODE_NAME" } } { "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "9.678 ns" { clock_k1 {} clock_k1~combout {} xuanze:u5|b {} hour:u6|data[2] {} } { 0.000ns 0.000ns 3.025ns 3.863ns } { 0.000ns 1.132ns 0.740ns 0.918ns } "" } } { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "9.678 ns" { clock_k1 xuanze:u5|b hour:u6|data[0] } "NODE_NAME" } } { "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "9.678 ns" { clock_k1 {} clock_k1~combout {} xuanze:u5|b {} hour:u6|data[0] {} } { 0.000ns 0.000ns 3.025ns 3.863ns } { 0.000ns 1.132ns 0.740ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "hour.vhd" "" { Text "E:/闹钟模块/签到器clock/hour.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "hour.vhd" "" { Text "E:/闹钟模块/签到器clock/hour.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "5.565 ns" { hour:u6|data[0] hour:u6|process0~53 hour:u6|process0~55 hour:u6|data[2] } "NODE_NAME" } } { "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "5.565 ns" { hour:u6|data[0] {} hour:u6|process0~53 {} hour:u6|process0~55 {} hour:u6|data[2] {} } { 0.000ns 1.347ns 0.794ns 1.195ns } { 0.000ns 0.914ns 0.511ns 0.804ns } "" } } { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "9.678 ns" { clock_k1 xuanze:u5|b hour:u6|data[2] } "NODE_NAME" } } { "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "9.678 ns" { clock_k1 {} clock_k1~combout {} xuanze:u5|b {} hour:u6|data[2] {} } { 0.000ns 0.000ns 3.025ns 3.863ns } { 0.000ns 1.132ns 0.740ns 0.918ns } "" } } { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "9.678 ns" { clock_k1 xuanze:u5|b hour:u6|data[0] } "NODE_NAME" } } { "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "9.678 ns" { clock_k1 {} clock_k1~combout {} xuanze:u5|b {} hour:u6|data[0] {} } { 0.000ns 0.000ns 3.025ns 3.863ns } { 0.000ns 1.132ns 0.740ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clock_666M 152 " "Warning: Circuit may not operate. Detected 152 non-operational path(s) clocked by clock \"clock_666M\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "hour:u6\|data\[0\] hour:u6\|data\[0\] clock_666M 10.044 ns " "Info: Found hold time violation between source  pin or register \"hour:u6\|data\[0\]\" and destination pin or register \"hour:u6\|data\[0\]\" for clock \"clock_666M\" (Hold time is 10.044 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "11.989 ns + Largest " "Info: + Largest clock skew is 11.989 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_666M destination 22.960 ns + Longest register " "Info: + Longest clock path from clock \"clock_666M\" to destination register is 22.960 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clock_666M 1 CLK PIN_18 26 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 26; CLK Node = 'clock_666M'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_666M } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/闹钟模块/签到器clock/clock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns divide_clock:u0\|Clk_se 2 REG LC_X10_Y7_N6 12 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y7_N6; Fanout = 12; REG Node = 'divide_clock:u0\|Clk_se'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clock_666M divide_clock:u0|Clk_se } "NODE_NAME" } } { "divide_clock.vhd" "" { Text "E:/闹钟模块/签到器clock/divide_clock.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.811 ns) + CELL(1.294 ns) 10.300 ns count:u2\|c2 3 REG LC_X11_Y6_N2 2 " "Info: 3: + IC(4.811 ns) + CELL(1.294 ns) = 10.300 ns; Loc. = LC_X11_Y6_N2; Fanout = 2; REG Node = 'count:u2\|c2'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "6.105 ns" { divide_clock:u0|Clk_se count:u2|c2 } "NODE_NAME" } } { "count.vhd" "" { Text "E:/闹钟模块/签到器clock/count.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.935 ns) + CELL(0.740 ns) 11.975 ns xuanze:u3\|b 4 COMB LC_X11_Y6_N7 9 " "Info: 4: + IC(0.935 ns) + CELL(0.740 ns) = 11.975 ns; Loc. = LC_X11_Y6_N7; Fanout = 9; COMB Node = 'xuanze:u3\|b'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "1.675 ns" { count:u2|c2 xuanze:u3|b } "NODE_NAME" } } { "xuanze.vhd" "" { Text "E:/闹钟模块/签到器clock/xuanze.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.728 ns) + CELL(1.294 ns) 16.997 ns count:u4\|c2 5 REG LC_X11_Y7_N2 2 " "Info: 5: + IC(3.728 ns) + CELL(1.294 ns) = 16.997 ns; Loc. = LC_X11_Y7_N2; Fanout = 2; REG Node = 'count:u4\|c2'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "5.022 ns" { xuanze:u3|b count:u4|c2 } "NODE_NAME" } } { "count.vhd" "" { Text "E:/闹钟模块/签到器clock/count.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.982 ns) + CELL(0.200 ns) 18.179 ns xuanze:u5\|b 6 COMB LC_X11_Y7_N5 9 " "Info: 6: + IC(0.982 ns) + CELL(0.200 ns) = 18.179 ns; Loc. = LC_X11_Y7_N5; Fanout = 9; COMB Node = 'xuanze:u5\|b'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "1.182 ns" { count:u4|c2 xuanze:u5|b } "NODE_NAME" } } { "xuanze.vhd" "" { Text "E:/闹钟模块/签到器clock/xuanze.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.863 ns) + CELL(0.918 ns) 22.960 ns hour:u6\|data\[0\] 7 REG LC_X10_Y9_N7 9 " "Info: 7: + IC(3.863 ns) + CELL(0.918 ns) = 22.960 ns; Loc. = LC_X10_Y9_N7; Fanout = 9; REG Node = 'hour:u6\|data\[0\]'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "4.781 ns" { xuanze:u5|b hour:u6|data[0] } "NODE_NAME" } } { "hour.vhd" "" { Text "E:/闹钟模块/签到器clock/hour.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.903 ns ( 30.07 % ) " "Info: Total cell delay = 6.903 ns ( 30.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "16.057 ns ( 69.93 % ) " "Info: Total interconnect delay = 16.057 ns ( 69.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "22.960 ns" { clock_666M divide_clock:u0|Clk_se count:u2|c2 xuanze:u3|b count:u4|c2 xuanze:u5|b hour:u6|data[0] } "NODE_NAME" } } { "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "22.960 ns" { clock_666M {} clock_666M~combout {} divide_clock:u0|Clk_se {} count:u2|c2 {} xuanze:u3|b {} count:u4|c2 {} xuanze:u5|b {} hour:u6|data[0] {} } { 0.000ns 0.000ns 1.738ns 4.811ns 0.935ns 3.728ns 0.982ns 3.863ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.740ns 1.294ns 0.200ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_666M source 10.971 ns - Shortest register " "Info: - Shortest clock path from clock \"clock_666M\" to source register is 10.971 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clock_666M 1 CLK PIN_18 26 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 26; CLK Node = 'clock_666M'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_666M } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/闹钟模块/签到器clock/clock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns divide_clock:u0\|Clk_se 2 REG LC_X10_Y7_N6 12 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y7_N6; Fanout = 12; REG Node = 'divide_clock:u0\|Clk_se'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clock_666M divide_clock:u0|Clk_se } "NODE_NAME" } } { "divide_clock.vhd" "" { Text "E:/闹钟模块/签到器clock/divide_clock.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.484 ns) + CELL(0.511 ns) 6.190 ns xuanze:u5\|b 3 COMB LC_X11_Y7_N5 9 " "Info: 3: + IC(1.484 ns) + CELL(0.511 ns) = 6.190 ns; Loc. = LC_X11_Y7_N5; Fanout = 9; COMB Node = 'xuanze:u5\|b'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "1.995 ns" { divide_clock:u0|Clk_se xuanze:u5|b } "NODE_NAME" } } { "xuanze.vhd" "" { Text "E:/闹钟模块/签到器clock/xuanze.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.863 ns) + CELL(0.918 ns) 10.971 ns hour:u6\|data\[0\] 4 REG LC_X10_Y9_N7 9 " "Info: 4: + IC(3.863 ns) + CELL(0.918 ns) = 10.971 ns; Loc. = LC_X10_Y9_N7; Fanout = 9; REG Node = 'hour:u6\|data\[0\]'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "4.781 ns" { xuanze:u5|b hour:u6|data[0] } "NODE_NAME" } } { "hour.vhd" "" { Text "E:/闹钟模块/签到器clock/hour.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.886 ns ( 35.42 % ) " "Info: Total cell delay = 3.886 ns ( 35.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.085 ns ( 64.58 % ) " "Info: Total interconnect delay = 7.085 ns ( 64.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "10.971 ns" { clock_666M divide_clock:u0|Clk_se xuanze:u5|b hour:u6|data[0] } "NODE_NAME" } } { "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "10.971 ns" { clock_666M {} clock_666M~combout {} divide_clock:u0|Clk_se {} xuanze:u5|b {} hour:u6|data[0] {} } { 0.000ns 0.000ns 1.738ns 1.484ns 3.863ns } { 0.000ns 1.163ns 1.294ns 0.511ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "22.960 ns" { clock_666M divide_clock:u0|Clk_se count:u2|c2 xuanze:u3|b count:u4|c2 xuanze:u5|b hour:u6|data[0] } "NODE_NAME" } } { "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "22.960 ns" { clock_666M {} clock_666M~combout {} divide_clock:u0|Clk_se {} count:u2|c2 {} xuanze:u3|b {} count:u4|c2 {} xuanze:u5|b {} hour:u6|data[0] {} } { 0.000ns 0.000ns 1.738ns 4.811ns 0.935ns 3.728ns 0.982ns 3.863ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.740ns 1.294ns 0.200ns 0.918ns } "" } } { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "10.971 ns" { clock_666M divide_clock:u0|Clk_se xuanze:u5|b hour:u6|data[0] } "NODE_NAME" } } { "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus72/quartus/bin/Technology_Viewer.qrui" "10.971 ns" { clock_666M {} clock_666M~combout {} divide_clock:u0|Clk_se {} xuanze:u5|b {} hour:u6|data[0] {} } { 0.000ns 0.000ns 1.738ns 1.484ns 3.863ns } { 0.000ns 1.163ns 1.294ns 0.511ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "hour.vhd" "" { Text "E:/闹钟模块/签到器clock/hour.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.790 ns - Shortest register register " "Info: - Shortest register to register delay is 1.790 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns hour:u6\|data\[0\] 1 REG LC_X10_Y9_N7 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y9_N7; Fanout = 9; REG Node = 'hour:u6\|data\[0\]'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { hour:u6|data[0] } "NODE_NAME" } } { "hour.vhd" "" { Text "E:/闹钟模块/签到器clock/hour.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.986 ns) + CELL(0.804 ns) 1.790 ns hour:u6\|data\[0\] 2 REG LC_X10_Y9_N7 9 " "Info: 2: + IC(0.986 ns) + CELL(0.804 ns) = 1.790 ns; Loc. = LC_X10_Y9_N7; Fanout = 9; REG Node = 'hour:u6\|data\[0\]'" {  } { { "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "1.790 ns" { hou