music_work.vhd

来自「基于CPLD的签到器的设计」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;

entity music_work is
    port
    (
        clock:in std_logic;
        en:in std_logic_vector(1 downto 0);
        clock_out:out std_logic
    );
end entity music_work;

architecture act of music_work is
begin
process(en)
begin
   if (en="01") then
      clock_out<='1';
   elsif (en="10") then
      clock_out<=clock;
   else clock_out<='0';
   end if;
end process;
end act;