even_division.hier_info

任意基数分频VERILOG代码

|even_division
reset => cnt1~16.OUTPUTSELECT
reset => cnt1~17.OUTPUTSELECT
reset => cnt1~18.OUTPUTSELECT
reset => cnt1~19.OUTPUTSELECT
reset => cnt1~20.OUTPUTSELECT
reset => cnt1~21.OUTPUTSELECT
reset => cnt1~22.OUTPUTSELECT
reset => cnt1~23.OUTPUTSELECT
reset => clk_temp1~2.OUTPUTSELECT
reset => cnt2~16.OUTPUTSELECT
reset => cnt2~17.OUTPUTSELECT
reset => cnt2~18.OUTPUTSELECT
reset => cnt2~19.OUTPUTSELECT
reset => cnt2~20.OUTPUTSELECT
reset => cnt2~21.OUTPUTSELECT
reset => cnt2~22.OUTPUTSELECT
reset => cnt2~23.OUTPUTSELECT
reset => clk_temp2~2.OUTPUTSELECT
clk => cnt1[6].CLK
clk => cnt1[5].CLK
clk => cnt1[4].CLK
clk => cnt1[3].CLK
clk => cnt1[2].CLK
clk => cnt1[1].CLK
clk => cnt1[0].CLK
clk => clk_temp1.CLK
clk => cnt1[7].CLK
clk => cnt2[6].CLK
clk => cnt2[5].CLK
clk => cnt2[4].CLK
clk => cnt2[3].CLK
clk => cnt2[2].CLK
clk => cnt2[1].CLK
clk => cnt2[0].CLK
clk => clk_temp2.CLK
clk => cnt2[7].CLK
clk_out <= clk_out~0.DB_MAX_OUTPUT_PORT_TYPE