even_division.tan.rpt

任意基数分频VERILOG代码

; N/A   ; None         ; 6.345 ns   ; reset ; cnt1[0]   ; clk      ;
; N/A   ; None         ; 6.345 ns   ; reset ; cnt1[1]   ; clk      ;
; N/A   ; None         ; 6.345 ns   ; reset ; cnt1[2]   ; clk      ;
; N/A   ; None         ; 6.345 ns   ; reset ; cnt1[3]   ; clk      ;
; N/A   ; None         ; 6.345 ns   ; reset ; cnt1[4]   ; clk      ;
; N/A   ; None         ; 6.345 ns   ; reset ; cnt1[5]   ; clk      ;
; N/A   ; None         ; 6.345 ns   ; reset ; cnt1[6]   ; clk      ;
; N/A   ; None         ; 6.345 ns   ; reset ; cnt1[7]   ; clk      ;
; N/A   ; None         ; 4.680 ns   ; reset ; clk_temp2 ; clk      ;
; N/A   ; None         ; 4.397 ns   ; reset ; clk_temp1 ; clk      ;
+-------+--------------+------------+-------+-----------+----------+


+----------------------------------------------------------------------+
; tco                                                                  ;
+-------+--------------+------------+-----------+---------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To      ; From Clock ;
+-------+--------------+------------+-----------+---------+------------+
; N/A   ; None         ; 7.814 ns   ; clk_temp2 ; clk_out ; clk        ;
; N/A   ; None         ; 7.602 ns   ; clk_temp1 ; clk_out ; clk        ;
+-------+--------------+------------+-----------+---------+------------+


+------------------------------------------------------------------------+
; th                                                                     ;
+---------------+-------------+-----------+-------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To        ; To Clock ;
+---------------+-------------+-----------+-------+-----------+----------+
; N/A           ; None        ; -4.345 ns ; reset ; clk_temp1 ; clk      ;
; N/A           ; None        ; -4.628 ns ; reset ; clk_temp2 ; clk      ;
; N/A           ; None        ; -6.293 ns ; reset ; cnt1[0]   ; clk      ;
; N/A           ; None        ; -6.293 ns ; reset ; cnt1[1]   ; clk      ;
; N/A           ; None        ; -6.293 ns ; reset ; cnt1[2]   ; clk      ;
; N/A           ; None        ; -6.293 ns ; reset ; cnt1[3]   ; clk      ;
; N/A           ; None        ; -6.293 ns ; reset ; cnt1[4]   ; clk      ;
; N/A           ; None        ; -6.293 ns ; reset ; cnt1[5]   ; clk      ;
; N/A           ; None        ; -6.293 ns ; reset ; cnt1[6]   ; clk      ;
; N/A           ; None        ; -6.293 ns ; reset ; cnt1[7]   ; clk      ;
; N/A           ; None        ; -6.773 ns ; reset ; cnt2[0]   ; clk      ;
; N/A           ; None        ; -6.773 ns ; reset ; cnt2[1]   ; clk      ;
; N/A           ; None        ; -6.773 ns ; reset ; cnt2[2]   ; clk      ;
; N/A           ; None        ; -6.773 ns ; reset ; cnt2[3]   ; clk      ;
; N/A           ; None        ; -6.773 ns ; reset ; cnt2[4]   ; clk      ;
; N/A           ; None        ; -6.773 ns ; reset ; cnt2[5]   ; clk      ;
; N/A           ; None        ; -6.773 ns ; reset ; cnt2[6]   ; clk      ;
; N/A           ; None        ; -6.773 ns ; reset ; cnt2[7]   ; clk      ;
+---------------+-------------+-----------+-------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Sep 27 17:14:14 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off even_division -c even_division --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 196.66 MHz between source register "cnt1[5]" and destination register "cnt1[0]" (period= 5.085 ns)
    Info: + Longest register to register delay is 4.824 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y16_N5; Fanout = 4; REG Node = 'cnt1[5]'
        Info: 2: + IC(0.785 ns) + CELL(0.590 ns) = 1.375 ns; Loc. = LC_X16_Y16_N9; Fanout = 1; COMB Node = 'Equal0~111'
        Info: 3: + IC(0.455 ns) + CELL(0.292 ns) = 2.122 ns; Loc. = LC_X16_Y16_N8; Fanout = 2; COMB Node = 'Equal0~112'
        Info: 4: + IC(0.757 ns) + CELL(0.114 ns) = 2.993 ns; Loc. = LC_X15_Y16_N7; Fanout = 8; COMB Node = 'cnt1[6]~188'
        Info: 5: + IC(0.719 ns) + CELL(1.112 ns) = 4.824 ns; Loc. = LC_X16_Y16_N0; Fanout = 5; REG Node = 'cnt1[0]'
        Info: Total cell delay = 2.108 ns ( 43.70 % )
        Info: Total interconnect delay = 2.716 ns ( 56.30 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.954 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 18; CLK Node = 'clk'
            Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X16_Y16_N0; Fanout = 5; REG Node = 'cnt1[0]'
            Info: Total cell delay = 2.180 ns ( 73.80 % )
            Info: Total interconnect delay = 0.774 ns ( 26.20 % )
        Info: - Longest clock path from clock "clk" to source register is 2.954 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 18; CLK Node = 'clk'
            Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X16_Y16_N5; Fanout = 4; REG Node = 'cnt1[5]'
            Info: Total cell delay = 2.180 ns ( 73.80 % )
            Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "cnt2[0]" (data pin = "reset", clock pin = "clk") is 6.825 ns
    Info: + Longest pin to register delay is 9.742 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_217; Fanout = 4; PIN Node = 'reset'
        Info: 2: + IC(5.841 ns) + CELL(0.590 ns) = 7.906 ns; Loc. = LC_X15_Y16_N8; Fanout = 8; COMB Node = 'cnt2[7]~188'
        Info: 3: + IC(0.724 ns) + CELL(1.112 ns) = 9.742 ns; Loc. = LC_X14_Y16_N0; Fanout = 5; REG Node = 'cnt2[0]'
        Info: Total cell delay = 3.177 ns ( 32.61 % )
        Info: Total interconnect delay = 6.565 ns ( 67.39 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 18; CLK Node = 'clk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X14_Y16_N0; Fanout = 5; REG Node = 'cnt2[0]'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
Info: tco from clock "clk" to destination pin "clk_out" through register "clk_temp2" is 7.814 ns
    Info: + Longest clock path from clock "clk" to source register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 18; CLK Node = 'clk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X15_Y16_N4; Fanout = 2; REG Node = 'clk_temp2'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.636 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y16_N4; Fanout = 2; REG Node = 'clk_temp2'
        Info: 2: + IC(0.562 ns) + CELL(0.292 ns) = 0.854 ns; Loc. = LC_X15_Y16_N6; Fanout = 1; COMB Node = 'clk_out~0'
        Info: 3: + IC(1.674 ns) + CELL(2.108 ns) = 4.636 ns; Loc. = PIN_214; Fanout = 0; PIN Node = 'clk_out'
        Info: Total cell delay = 2.400 ns ( 51.77 % )
        Info: Total interconnect delay = 2.236 ns ( 48.23 % )
Info: th for register "clk_temp1" (data pin = "reset", clock pin = "clk") is -4.345 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 18; CLK Node = 'clk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X15_Y16_N5; Fanout = 2; REG Node = 'clk_temp1'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 7.314 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_217; Fanout = 4; PIN Node = 'reset'
        Info: 2: + IC(5.530 ns) + CELL(0.309 ns) = 7.314 ns; Loc. = LC_X15_Y16_N5; Fanout = 2; REG Node = 'clk_temp1'
        Info: Total cell delay = 1.784 ns ( 24.39 % )
        Info: Total interconnect delay = 5.530 ns ( 75.61 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Sep 27 17:14:14 2008
    Info: Elapsed time: 00:00:01