even_division.v

任意基数分频VERILOG代码

module even_division(reset,clk,clk_out);
 input clk,reset;
 output clk_out;
 reg  clk_out;
 reg  [7:0]cnt1;
 reg  [7:0]cnt2;
 reg  clk_temp1;
 reg  clk_temp2;
parameter N=7;
  
  always @(posedge clk)
   if(!reset)
    begin
     cnt1<=0;
     clk_temp1<=0;
    end
   else
    begin
     if(cnt1==(N-1)/2)
      begin
       cnt1<=cnt1+1'b1;
       clk_temp1<=~clk_temp1;
      end
     else if(cnt1==N-1)
       begin
        cnt1<=0;
        clk_temp1<=~clk_temp1;
       end
     else
      cnt1<=cnt1+1'b1; 
    end 
    
  always @(negedge clk)
   if(!reset)
    begin
     cnt2<=0;
     clk_temp2<=0;
    end
   else
    begin
     if(cnt2==(N-1)/2)
      begin
       cnt2<=cnt2+1'b1;
       clk_temp2<=~clk_temp2;
      end
     else if(cnt2==N-1)
       begin
        cnt2<=0;
        clk_temp2<=~clk_temp2;
       end
     else
      cnt2<=cnt2+1'b1; 
    end
    
  always 
   begin
    clk_out<=clk_temp1||clk_temp2;
   end  
endmodule