colorbar.map.qmsg

基于EPM1270的VGA显示器接口源码Verilog

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 vga_vl.v(121) " "Warning: Verilog HDL assignment warning at vga_vl.v(121): truncated value with size 32 to match size of target (11)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 121 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_vl.v(126) " "Warning: Verilog HDL assignment warning at vga_vl.v(126): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 126 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_vl.v(128) " "Warning: Verilog HDL assignment warning at vga_vl.v(128): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 128 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_vl.v(130) " "Warning: Verilog HDL assignment warning at vga_vl.v(130): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 130 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_vl.v(135) " "Warning: Verilog HDL assignment warning at vga_vl.v(135): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 135 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_vl.v(137) " "Warning: Verilog HDL assignment warning at vga_vl.v(137): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 137 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_vl.v(139) " "Warning: Verilog HDL assignment warning at vga_vl.v(139): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(144) " "Warning: Verilog HDL assignment warning at vga_vl.v(144): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 144 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(149) " "Warning: Verilog HDL assignment warning at vga_vl.v(149): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 149 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(152) " "Warning: Verilog HDL assignment warning at vga_vl.v(152): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 152 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(155) " "Warning: Verilog HDL assignment warning at vga_vl.v(155): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 155 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(158) " "Warning: Verilog HDL assignment warning at vga_vl.v(158): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 158 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(161) " "Warning: Verilog HDL assignment warning at vga_vl.v(161): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 161 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(164) " "Warning: Verilog HDL assignment warning at vga_vl.v(164): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 164 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(167) " "Warning: Verilog HDL assignment warning at vga_vl.v(167): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 167 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(169) " "Warning: Verilog HDL assignment warning at vga_vl.v(169): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 169 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(174) " "Warning: Verilog HDL assignment warning at vga_vl.v(174): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 174 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(177) " "Warning: Verilog HDL assignment warning at vga_vl.v(177): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 177 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(180) " "Warning: Verilog HDL assignment warning at vga_vl.v(180): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 180 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(183) " "Warning: Verilog HDL assignment warning at vga_vl.v(183): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 183 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(186) " "Warning: Verilog HDL assignment warning at vga_vl.v(186): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 186 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(189) " "Warning: Verilog HDL assignment warning at vga_vl.v(189): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 189 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(192) " "Warning: Verilog HDL assignment warning at vga_vl.v(192): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 192 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(194) " "Warning: Verilog HDL assignment warning at vga_vl.v(194): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 194 0 0 } }  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 91 -1 0 } } { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 67 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "72 " "Info: Implemented 72 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "65 " "Info: Implemented 65 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 45 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 45 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 16 16:23:58 2006 " "Info: Processing ended: Thu Feb 16 16:23:58 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}