colorbar.map.qmsg

基于EPM1270的VGA显示器接口源码Verilog

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 16 16:23:56 2006 " "Info: Processing started: Thu Feb 16 16:23:56 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ColorBar -c ColorBar " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ColorBar -c ColorBar" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/vga_vl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../src/vga_vl.v" { { "Info" "ISGN_ENTITY_NAME" "1 vga_vl " "Info: Found entity 1: vga_vl" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 58 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../Src/ColorBar.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../Src/ColorBar.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ColorBar " "Info: Found entity 1: ColorBar" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ColorBar " "Info: Elaborating entity \"ColorBar\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "H_PIXELS 32'b00000000000000000000001100100110 " "Warning: Can't find a definition for parameter H_PIXELS -- assuming 32'b00000000000000000000001100100110 was intended to be a quoted string" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 216 344 480 344 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "H_FRONTPORCH 32'b00000000000000000000000000100101 " "Warning: Can't find a definition for parameter H_FRONTPORCH -- assuming 32'b00000000000000000000000000100101 was intended to be a quoted string" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 216 344 480 344 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "H_SYNCTIME 32'b00000000000000000000000010000000 " "Warning: Can't find a definition for parameter H_SYNCTIME -- assuming 32'b00000000000000000000000010000000 was intended to be a quoted string" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 216 344 480 344 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "H_BACKPORCH 32'b00000000000000000000000001010101 " "Warning: Can't find a definition for parameter H_BACKPORCH -- assuming 32'b00000000000000000000000001010101 was intended to be a quoted string" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 216 344 480 344 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "H_SYNCSTART 32'b00000000000000000000001101001011 " "Warning: Can't find a definition for parameter H_SYNCSTART -- assuming 32'b00000000000000000000001101001011 was intended to be a quoted string" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 216 344 480 344 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "H_SYNCEND 32'b00000000000000000000001111001011 " "Warning: Can't find a definition for parameter H_SYNCEND -- assuming 32'b00000000000000000000001111001011 was intended to be a quoted string" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 216 344 480 344 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "H_PERIOD 32'b00000000000000000000010000100000 " "Warning: Can't find a definition for parameter H_PERIOD -- assuming 32'b00000000000000000000010000100000 was intended to be a quoted string" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 216 344 480 344 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "V_LINES 32'b00000000000000000000001001011100 " "Warning: Can't find a definition for parameter V_LINES -- assuming 32'b00000000000000000000001001011100 was intended to be a quoted string" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 216 344 480 344 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "V_SYNCTIME 32'b00000000000000000000000000000100 " "Warning: Can't find a definition for parameter V_SYNCTIME -- assuming 32'b00000000000000000000000000000100 was intended to be a quoted string" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 216 344 480 344 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "V_BACKPORCH 32'b00000000000000000000000000010101 " "Warning: Can't find a definition for parameter V_BACKPORCH -- assuming 32'b00000000000000000000000000010101 was intended to be a quoted string" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 216 344 480 344 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "V_SYNCSTART 32'b00000000000000000000001001011011 " "Warning: Can't find a definition for parameter V_SYNCSTART -- assuming 32'b00000000000000000000001001011011 was intended to be a quoted string" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 216 344 480 344 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "V_SYNCEND 32'b00000000000000000000001001011111 " "Warning: Can't find a definition for parameter V_SYNCEND -- assuming 32'b00000000000000000000001001011111 was intended to be a quoted string" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 216 344 480 344 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "V_PERIOD 32'b00000000000000000000001001110100 " "Warning: Can't find a definition for parameter V_PERIOD -- assuming 32'b00000000000000000000001001110100 was intended to be a quoted string" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 216 344 480 344 "inst" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_vl vga_vl:inst " "Info: Elaborating entity \"vga_vl\" for hierarchy \"vga_vl:inst\"" {  } { { "../Src/ColorBar.bdf" "inst" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 216 344 480 344 "inst" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 vga_vl.v(96) " "Warning: Verilog HDL assignment warning at vga_vl.v(96): truncated value with size 32 to match size of target (11)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 96 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 vga_vl.v(98) " "Warning: Verilog HDL assignment warning at vga_vl.v(98): truncated value with size 32 to match size of target (11)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 98 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 vga_vl.v(100) " "Warning: Verilog HDL assignment warning at vga_vl.v(100): truncated value with size 32 to match size of target (11)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 100 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_vl.v(105) " "Warning: Verilog HDL assignment warning at vga_vl.v(105): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 105 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_vl.v(107) " "Warning: Verilog HDL assignment warning at vga_vl.v(107): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 107 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_vl.v(109) " "Warning: Verilog HDL assignment warning at vga_vl.v(109): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 109 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 vga_vl.v(117) " "Warning: Verilog HDL assignment warning at vga_vl.v(117): truncated value with size 32 to match size of target (11)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 117 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 vga_vl.v(119) " "Warning: Verilog HDL assignment warning at vga_vl.v(119): truncated value with size 32 to match size of target (11)" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 119 0 0 } }  } 0}