colorbar.hier_info

基于EPM1270的VGA显示器接口源码Verilog

|ColorBar
VGA_HS <= vga_vl:inst.hsync
rst => vga_vl:inst.resetn
clk => vga_vl:inst.clock
VGA_VS <= vga_vl:inst.vsync
VGA_RGB[0] <= vga_vl:inst.pixel[0]
VGA_RGB[1] <= vga_vl:inst.pixel[1]
VGA_RGB[2] <= vga_vl:inst.pixel[2]


|ColorBar|vga_vl:inst
resetn => hcnt[9].ACLR
resetn => hcnt[8].ACLR
resetn => hcnt[7].ACLR
resetn => hcnt[6].ACLR
resetn => hcnt[5].ACLR
resetn => hcnt[4].ACLR
resetn => hcnt[3].ACLR
resetn => hcnt[2].ACLR
resetn => hcnt[1].ACLR
resetn => hcnt[0].ACLR
resetn => vsync~reg0.PRESET
resetn => hcnt[10].ACLR
resetn => hsyncint.PRESET
resetn => enable.ACLR
resetn => vcnt[9].ACLR
resetn => vcnt[8].ACLR
resetn => vcnt[7].ACLR
resetn => vcnt[6].ACLR
resetn => vcnt[5].ACLR
resetn => vcnt[4].ACLR
resetn => vcnt[3].ACLR
resetn => vcnt[2].ACLR
resetn => vcnt[1].ACLR
resetn => vcnt[0].ACLR
resetn => vcnt[10].ACLR
clock => hcnt[9].CLK
clock => hcnt[8].CLK
clock => hcnt[7].CLK
clock => hcnt[6].CLK
clock => hcnt[5].CLK
clock => hcnt[4].CLK
clock => hcnt[3].CLK
clock => hcnt[2].CLK
clock => hcnt[1].CLK
clock => hcnt[0].CLK
clock => hsyncint.CLK
clock => enable.CLK
clock => hcnt[10].CLK
orient => pixel~34.OUTPUTSELECT
orient => pixel~35.OUTPUTSELECT
orient => pixel~36.OUTPUTSELECT
hsync <= hsyncint.DB_MAX_OUTPUT_PORT_TYPE
vsync <= vsync~reg0.DB_MAX_OUTPUT_PORT_TYPE
pixel[0] <= pixel~39.DB_MAX_OUTPUT_PORT_TYPE
pixel[1] <= pixel~38.DB_MAX_OUTPUT_PORT_TYPE
pixel[2] <= pixel~37.DB_MAX_OUTPUT_PORT_TYPE
blank <= enable.DB_MAX_OUTPUT_PORT_TYPE