colorbar.fit.qmsg

基于EPM1270的VGA显示器接口源码Verilog

{ "Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Info: Moving registers into LUTs to improve timing and density" {  } {  } 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "" "Info: Finished moving registers into LUTs" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "11.622 ns register pin " "Info: Estimated most critical path is register to pin delay of 11.622 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_vl:inst\|hcnt\[7\] 1 REG LAB_X9_Y8 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X9_Y8; Fanout = 13; REG Node = 'vga_vl:inst\|hcnt\[7\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "" { vga_vl:inst|hcnt[7] } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 90 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.740 ns) 1.813 ns vga_vl:inst\|LessThan~1898 2 COMB LAB_X8_Y8 2 " "Info: 2: + IC(1.073 ns) + CELL(0.740 ns) = 1.813 ns; Loc. = LAB_X8_Y8; Fanout = 2; COMB Node = 'vga_vl:inst\|LessThan~1898'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "1.813 ns" { vga_vl:inst|hcnt[7] vga_vl:inst|LessThan~1898 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.914 ns) 3.449 ns vga_vl:inst\|LessThan~1900 3 COMB LAB_X7_Y8 2 " "Info: 3: + IC(0.722 ns) + CELL(0.914 ns) = 3.449 ns; Loc. = LAB_X7_Y8; Fanout = 2; COMB Node = 'vga_vl:inst\|LessThan~1900'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "1.636 ns" { vga_vl:inst|LessThan~1898 vga_vl:inst|LessThan~1900 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.672 ns) + CELL(0.511 ns) 4.632 ns vga_vl:inst\|pixel\[0\]~1262 4 COMB LAB_X7_Y8 1 " "Info: 4: + IC(0.672 ns) + CELL(0.511 ns) = 4.632 ns; Loc. = LAB_X7_Y8; Fanout = 1; COMB Node = 'vga_vl:inst\|pixel\[0\]~1262'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "1.183 ns" { vga_vl:inst|LessThan~1900 vga_vl:inst|pixel[0]~1262 } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 68 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.125 ns) + CELL(0.511 ns) 6.268 ns vga_vl:inst\|pixel\[0\]~1263 5 COMB LAB_X6_Y8 1 " "Info: 5: + IC(1.125 ns) + CELL(0.511 ns) = 6.268 ns; Loc. = LAB_X6_Y8; Fanout = 1; COMB Node = 'vga_vl:inst\|pixel\[0\]~1263'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "1.636 ns" { vga_vl:inst|pixel[0]~1262 vga_vl:inst|pixel[0]~1263 } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 68 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.269 ns) + CELL(0.914 ns) 7.451 ns vga_vl:inst\|pixel\[0\]~1267 6 COMB LAB_X6_Y8 1 " "Info: 6: + IC(0.269 ns) + CELL(0.914 ns) = 7.451 ns; Loc. = LAB_X6_Y8; Fanout = 1; COMB Node = 'vga_vl:inst\|pixel\[0\]~1267'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "1.183 ns" { vga_vl:inst|pixel[0]~1263 vga_vl:inst|pixel[0]~1267 } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 68 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.849 ns) + CELL(2.322 ns) 11.622 ns VGA_RGB\[0\] 7 PIN PIN_137 0 " "Info: 7: + IC(1.849 ns) + CELL(2.322 ns) = 11.622 ns; Loc. = PIN_137; Fanout = 0; PIN Node = 'VGA_RGB\[0\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "4.171 ns" { vga_vl:inst|pixel[0]~1267 VGA_RGB[0] } "NODE_NAME" } "" } } { "../Src/ColorBar.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 288 608 784 304 "VGA_RGB\[2..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.912 ns 50.87 % " "Info: Total cell delay = 5.912 ns ( 50.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.710 ns 49.13 % " "Info: Total interconnect delay = 5.710 ns ( 49.13 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "11.622 ns" { vga_vl:inst|hcnt[7] vga_vl:inst|LessThan~1898 vga_vl:inst|LessThan~1900 vga_vl:inst|pixel[0]~1262 vga_vl:inst|pixel[0]~1263 vga_vl:inst|pixel[0]~1267 VGA_RGB[0] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 1 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 1%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "Info: Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and/or routability requirements required full optimization" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 16 16:24:02 2006 " "Info: Processing ended: Thu Feb 16 16:24:02 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}