colorbar.tan.qmsg

基于EPM1270的VGA显示器接口源码Verilog

{ "Info" "ITDB_FULL_TCO_RESULT" "clk VGA_RGB\[0\] vga_vl:inst\|hcnt\[7\] 18.656 ns register " "Info: tco from clock \"clk\" to destination pin \"VGA_RGB\[0\]\" through register \"vga_vl:inst\|hcnt\[7\]\" is 18.656 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.732 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.732 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 13 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 13; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "../Src/ColorBar.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 24 104 272 40 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.682 ns) + CELL(0.918 ns) 6.732 ns vga_vl:inst\|hcnt\[7\] 2 REG LC_X9_Y8_N2 13 " "Info: 2: + IC(4.682 ns) + CELL(0.918 ns) = 6.732 ns; Loc. = LC_X9_Y8_N2; Fanout = 13; REG Node = 'vga_vl:inst\|hcnt\[7\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "5.600 ns" { clk vga_vl:inst|hcnt[7] } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 90 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.45 % " "Info: Total cell delay = 2.050 ns ( 30.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.682 ns 69.55 % " "Info: Total interconnect delay = 4.682 ns ( 69.55 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "6.732 ns" { clk vga_vl:inst|hcnt[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.732 ns" { clk clk~combout vga_vl:inst|hcnt[7] } { 0.000ns 0.000ns 4.682ns } { 0.000ns 1.132ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 90 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.548 ns + Longest register pin " "Info: + Longest register to pin delay is 11.548 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_vl:inst\|hcnt\[7\] 1 REG LC_X9_Y8_N2 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y8_N2; Fanout = 13; REG Node = 'vga_vl:inst\|hcnt\[7\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "" { vga_vl:inst|hcnt[7] } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 90 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.352 ns) + CELL(0.740 ns) 2.092 ns vga_vl:inst\|LessThan~1898 2 COMB LC_X8_Y8_N0 2 " "Info: 2: + IC(1.352 ns) + CELL(0.740 ns) = 2.092 ns; Loc. = LC_X8_Y8_N0; Fanout = 2; COMB Node = 'vga_vl:inst\|LessThan~1898'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "2.092 ns" { vga_vl:inst|hcnt[7] vga_vl:inst|LessThan~1898 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.855 ns) + CELL(0.200 ns) 4.147 ns vga_vl:inst\|LessThan~1900 3 COMB LC_X7_Y8_N7 2 " "Info: 3: + IC(1.855 ns) + CELL(0.200 ns) = 4.147 ns; Loc. = LC_X7_Y8_N7; Fanout = 2; COMB Node = 'vga_vl:inst\|LessThan~1900'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "2.055 ns" { vga_vl:inst|LessThan~1898 vga_vl:inst|LessThan~1900 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.759 ns) + CELL(0.511 ns) 5.417 ns vga_vl:inst\|pixel\[0\]~1262 4 COMB LC_X7_Y8_N4 1 " "Info: 4: + IC(0.759 ns) + CELL(0.511 ns) = 5.417 ns; Loc. = LC_X7_Y8_N4; Fanout = 1; COMB Node = 'vga_vl:inst\|pixel\[0\]~1262'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "1.270 ns" { vga_vl:inst|LessThan~1900 vga_vl:inst|pixel[0]~1262 } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 68 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.168 ns) + CELL(0.200 ns) 6.785 ns vga_vl:inst\|pixel\[0\]~1263 5 COMB LC_X6_Y8_N6 1 " "Info: 5: + IC(1.168 ns) + CELL(0.200 ns) = 6.785 ns; Loc. = LC_X6_Y8_N6; Fanout = 1; COMB Node = 'vga_vl:inst\|pixel\[0\]~1263'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "1.368 ns" { vga_vl:inst|pixel[0]~1262 vga_vl:inst|pixel[0]~1263 } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 68 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 7.290 ns vga_vl:inst\|pixel\[0\]~1267 6 COMB LC_X6_Y8_N7 1 " "Info: 6: + IC(0.305 ns) + CELL(0.200 ns) = 7.290 ns; Loc. = LC_X6_Y8_N7; Fanout = 1; COMB Node = 'vga_vl:inst\|pixel\[0\]~1267'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "0.505 ns" { vga_vl:inst|pixel[0]~1263 vga_vl:inst|pixel[0]~1267 } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 68 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.936 ns) + CELL(2.322 ns) 11.548 ns VGA_RGB\[0\] 7 PIN PIN_137 0 " "Info: 7: + IC(1.936 ns) + CELL(2.322 ns) = 11.548 ns; Loc. = PIN_137; Fanout = 0; PIN Node = 'VGA_RGB\[0\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "4.258 ns" { vga_vl:inst|pixel[0]~1267 VGA_RGB[0] } "NODE_NAME" } "" } } { "../Src/ColorBar.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 288 608 784 304 "VGA_RGB\[2..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.173 ns 36.14 % " "Info: Total cell delay = 4.173 ns ( 36.14 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.375 ns 63.86 % " "Info: Total interconnect delay = 7.375 ns ( 63.86 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "11.548 ns" { vga_vl:inst|hcnt[7] vga_vl:inst|LessThan~1898 vga_vl:inst|LessThan~1900 vga_vl:inst|pixel[0]~1262 vga_vl:inst|pixel[0]~1263 vga_vl:inst|pixel[0]~1267 VGA_RGB[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.548 ns" { vga_vl:inst|hcnt[7] vga_vl:inst|LessThan~1898 vga_vl:inst|LessThan~1900 vga_vl:inst|pixel[0]~1262 vga_vl:inst|pixel[0]~1263 vga_vl:inst|pixel[0]~1267 VGA_RGB[0] } { 0.000ns 1.352ns 1.855ns 0.759ns 1.168ns 0.305ns 1.936ns } { 0.000ns 0.740ns 0.200ns 0.511ns 0.200ns 0.200ns 2.322ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "6.732 ns" { clk vga_vl:inst|hcnt[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.732 ns" { clk clk~combout vga_vl:inst|hcnt[7] } { 0.000ns 0.000ns 4.682ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "11.548 ns" { vga_vl:inst|hcnt[7] vga_vl:inst|LessThan~1898 vga_vl:inst|LessThan~1900 vga_vl:inst|pixel[0]~1262 vga_vl:inst|pixel[0]~1263 vga_vl:inst|pixel[0]~1267 VGA_RGB[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.548 ns" { vga_vl:inst|hcnt[7] vga_vl:inst|LessThan~1898 vga_vl:inst|LessThan~1900 vga_vl:inst|pixel[0]~1262 vga_vl:inst|pixel[0]~1263 vga_vl:inst|pixel[0]~1267 VGA_RGB[0] } { 0.000ns 1.352ns 1.855ns 0.759ns 1.168ns 0.305ns 1.936ns } { 0.000ns 0.740ns 0.200ns 0.511ns 0.200ns 0.200ns 2.322ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 16 16:24:07 2006 " "Info: Processing ended: Thu Feb 16 16:24:07 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}