colorbar.tan.qmsg

基于EPM1270的VGA显示器接口源码Verilog

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 24 104 272 40 "clk" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "vga_vl:inst\|hsyncint " "Info: Detected ripple clock \"vga_vl:inst\|hsyncint\" as buffer" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 91 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "vga_vl:inst\|hsyncint" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register vga_vl:inst\|vcnt\[7\] register vga_vl:inst\|enable 45.29 MHz 22.08 ns Internal " "Info: Clock \"clk\" has Internal fmax of 45.29 MHz between source register \"vga_vl:inst\|vcnt\[7\]\" and destination register \"vga_vl:inst\|enable\" (period= 22.08 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.099 ns + Longest register register " "Info: + Longest register to register delay is 5.099 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_vl:inst\|vcnt\[7\] 1 REG LC_X7_Y6_N2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y6_N2; Fanout = 5; REG Node = 'vga_vl:inst\|vcnt\[7\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "" { vga_vl:inst|vcnt[7] } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 90 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.943 ns) + CELL(0.740 ns) 1.683 ns vga_vl:inst\|always4~151 2 COMB LC_X7_Y6_N9 2 " "Info: 2: + IC(0.943 ns) + CELL(0.740 ns) = 1.683 ns; Loc. = LC_X7_Y6_N9; Fanout = 2; COMB Node = 'vga_vl:inst\|always4~151'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "1.683 ns" { vga_vl:inst|vcnt[7] vga_vl:inst|always4~151 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.101 ns) + CELL(0.914 ns) 3.698 ns vga_vl:inst\|always4~152 3 COMB LC_X8_Y6_N2 1 " "Info: 3: + IC(1.101 ns) + CELL(0.914 ns) = 3.698 ns; Loc. = LC_X8_Y6_N2; Fanout = 1; COMB Node = 'vga_vl:inst\|always4~152'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "2.015 ns" { vga_vl:inst|always4~151 vga_vl:inst|always4~152 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 4.203 ns vga_vl:inst\|always4~153 4 COMB LC_X8_Y6_N3 1 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 4.203 ns; Loc. = LC_X8_Y6_N3; Fanout = 1; COMB Node = 'vga_vl:inst\|always4~153'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "0.505 ns" { vga_vl:inst|always4~152 vga_vl:inst|always4~153 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.591 ns) 5.099 ns vga_vl:inst\|enable 5 REG LC_X8_Y6_N4 5 " "Info: 5: + IC(0.305 ns) + CELL(0.591 ns) = 5.099 ns; Loc. = LC_X8_Y6_N4; Fanout = 5; REG Node = 'vga_vl:inst\|enable'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "0.896 ns" { vga_vl:inst|always4~153 vga_vl:inst|enable } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 91 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.445 ns 47.95 % " "Info: Total cell delay = 2.445 ns ( 47.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.654 ns 52.05 % " "Info: Total interconnect delay = 2.654 ns ( 52.05 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "5.099 ns" { vga_vl:inst|vcnt[7] vga_vl:inst|always4~151 vga_vl:inst|always4~152 vga_vl:inst|always4~153 vga_vl:inst|enable } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.099 ns" { vga_vl:inst|vcnt[7] vga_vl:inst|always4~151 vga_vl:inst|always4~152 vga_vl:inst|always4~153 vga_vl:inst|enable } { 0.000ns 0.943ns 1.101ns 0.305ns 0.305ns } { 0.000ns 0.740ns 0.914ns 0.200ns 0.591ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.232 ns - Smallest " "Info: - Smallest clock skew is -5.232 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.732 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 6.732 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 13 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 13; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "../Src/ColorBar.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 24 104 272 40 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.682 ns) + CELL(0.918 ns) 6.732 ns vga_vl:inst\|enable 2 REG LC_X8_Y6_N4 5 " "Info: 2: + IC(4.682 ns) + CELL(0.918 ns) = 6.732 ns; Loc. = LC_X8_Y6_N4; Fanout = 5; REG Node = 'vga_vl:inst\|enable'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "5.600 ns" { clk vga_vl:inst|enable } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 91 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.45 % " "Info: Total cell delay = 2.050 ns ( 30.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.682 ns 69.55 % " "Info: Total interconnect delay = 4.682 ns ( 69.55 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "6.732 ns" { clk vga_vl:inst|enable } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.732 ns" { clk clk~combout vga_vl:inst|enable } { 0.000ns 0.000ns 4.682ns } { 0.000ns 1.132ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 11.964 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 11.964 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 13 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 13; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "../Src/ColorBar.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 24 104 272 40 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.682 ns) + CELL(1.294 ns) 7.108 ns vga_vl:inst\|hsyncint 2 REG LC_X10_Y7_N4 13 " "Info: 2: + IC(4.682 ns) + CELL(1.294 ns) = 7.108 ns; Loc. = LC_X10_Y7_N4; Fanout = 13; REG Node = 'vga_vl:inst\|hsyncint'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "5.976 ns" { clk vga_vl:inst|hsyncint } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 91 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.938 ns) + CELL(0.918 ns) 11.964 ns vga_vl:inst\|vcnt\[7\] 3 REG LC_X7_Y6_N2 5 " "Info: 3: + IC(3.938 ns) + CELL(0.918 ns) = 11.964 ns; Loc. = LC_X7_Y6_N2; Fanout = 5; REG Node = 'vga_vl:inst\|vcnt\[7\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "4.856 ns" { vga_vl:inst|hsyncint vga_vl:inst|vcnt[7] } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 90 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns 27.95 % " "Info: Total cell delay = 3.344 ns ( 27.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.620 ns 72.05 % " "Info: Total interconnect delay = 8.620 ns ( 72.05 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "11.964 ns" { clk vga_vl:inst|hsyncint vga_vl:inst|vcnt[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.964 ns" { clk clk~combout vga_vl:inst|hsyncint vga_vl:inst|vcnt[7] } { 0.000ns 0.000ns 4.682ns 3.938ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "6.732 ns" { clk vga_vl:inst|enable } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.732 ns" { clk clk~combout vga_vl:inst|enable } { 0.000ns 0.000ns 4.682ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "11.964 ns" { clk vga_vl:inst|hsyncint vga_vl:inst|vcnt[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.964 ns" { clk clk~combout vga_vl:inst|hsyncint vga_vl:inst|vcnt[7] } { 0.000ns 0.000ns 4.682ns 3.938ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 90 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 91 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 90 -1 0 } } { "../src/vga_vl.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 91 -1 0 } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "5.099 ns" { vga_vl:inst|vcnt[7] vga_vl:inst|always4~151 vga_vl:inst|always4~152 vga_vl:inst|always4~153 vga_vl:inst|enable } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.099 ns" { vga_vl:inst|vcnt[7] vga_vl:inst|always4~151 vga_vl:inst|always4~152 vga_vl:inst|always4~153 vga_vl:inst|enable } { 0.000ns 0.943ns 1.101ns 0.305ns 0.305ns } { 0.000ns 0.740ns 0.914ns 0.200ns 0.591ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "6.732 ns" { clk vga_vl:inst|enable } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.732 ns" { clk clk~combout vga_vl:inst|enable } { 0.000ns 0.000ns 4.682ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/" "" "11.964 ns" { clk vga_vl:inst|hsyncint vga_vl:inst|vcnt[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.964 ns" { clk clk~combout vga_vl:inst|hsyncint vga_vl:inst|vcnt[7] } { 0.000ns 0.000ns 4.682ns 3.938ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0}