📄 colorbar.fit.rpt
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; Interconnect Resource Type ; Usage ;
+----------------------------+----------------------+
; C4s ; 26 / 2,870 ( < 1 % ) ;
; Direct links ; 37 / 3,938 ( < 1 % ) ;
; Global clocks ; 3 / 4 ( 75 % ) ;
; LAB clocks ; 10 / 72 ( 13 % ) ;
; LUT chains ; 7 / 1,143 ( < 1 % ) ;
; Local interconnects ; 91 / 3,938 ( 2 % ) ;
; R4s ; 33 / 2,832 ( 1 % ) ;
+----------------------------+----------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 5.91) ; Number of LABs (Total = 11) ;
+--------------------------------------------+------------------------------+
; 1 ; 2 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 4 ;
; 10 ; 2 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.45) ; Number of LABs (Total = 11) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 7 ;
; 1 Clock ; 7 ;
; 1 Sync. clear ; 2 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 5.91) ; Number of LABs (Total = 11) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 4 ;
; 10 ; 2 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 4.73) ; Number of LABs (Total = 11) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 4 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 1 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 2 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 8.09) ; Number of LABs (Total = 11) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 2 ;
; 5 ; 0 ;
; 6 ; 3 ;
; 7 ; 0 ;
; 8 ; 2 ;
; 9 ; 1 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 1 ;
; 13 ; 2 ;
+---------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Thu Feb 16 16:23:59 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ColorBar -c ColorBar
Info: Selected device EPM1270T144C5 for design "ColorBar"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EPM570T144C5 is compatible
Info: Device EPM570T144I5 is compatible
Info: Device EPM1270T144I5 is compatible
Info: Device EPM1270T144C5ES is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock
Info: Pin "clk" drives global clock, but is not placed in a dedicated clock pin position
Info: Automatically promoted some destinations of signal "vga_vl:inst|hsyncint" to use Global clock
Info: Destination "VGA_HS" may be non-global or may not use global clock
Info: Automatically promoted signal "rst" to use Global clock
Info: Pin "rst" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to pin delay of 11.622 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X9_Y8; Fanout = 13; REG Node = 'vga_vl:inst|hcnt[7]'
Info: 2: + IC(1.073 ns) + CELL(0.740 ns) = 1.813 ns; Loc. = LAB_X8_Y8; Fanout = 2; COMB Node = 'vga_vl:inst|LessThan~1898'
Info: 3: + IC(0.722 ns) + CELL(0.914 ns) = 3.449 ns; Loc. = LAB_X7_Y8; Fanout = 2; COMB Node = 'vga_vl:inst|LessThan~1900'
Info: 4: + IC(0.672 ns) + CELL(0.511 ns) = 4.632 ns; Loc. = LAB_X7_Y8; Fanout = 1; COMB Node = 'vga_vl:inst|pixel[0]~1262'
Info: 5: + IC(1.125 ns) + CELL(0.511 ns) = 6.268 ns; Loc. = LAB_X6_Y8; Fanout = 1; COMB Node = 'vga_vl:inst|pixel[0]~1263'
Info: 6: + IC(0.269 ns) + CELL(0.914 ns) = 7.451 ns; Loc. = LAB_X6_Y8; Fanout = 1; COMB Node = 'vga_vl:inst|pixel[0]~1267'
Info: 7: + IC(1.849 ns) + CELL(2.322 ns) = 11.622 ns; Loc. = PIN_137; Fanout = 0; PIN Node = 'VGA_RGB[0]'
Info: Total cell delay = 5.912 ns ( 50.87 % )
Info: Total interconnect delay = 5.710 ns ( 49.13 % )
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 1%.
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and/or routability requirements required full optimization
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Thu Feb 16 16:24:02 2006
Info: Elapsed time: 00:00:03
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