colorbar.tan.rpt

基于EPM1270的VGA显示器接口源码Verilog

; N/A   ; None         ; 18.656 ns  ; vga_vl:inst|hcnt[7]  ; VGA_RGB[0] ; clk        ;
; N/A   ; None         ; 18.547 ns  ; vga_vl:inst|hcnt[5]  ; VGA_RGB[0] ; clk        ;
; N/A   ; None         ; 18.501 ns  ; vga_vl:inst|hcnt[7]  ; VGA_RGB[1] ; clk        ;
; N/A   ; None         ; 18.478 ns  ; vga_vl:inst|hcnt[7]  ; VGA_RGB[2] ; clk        ;
; N/A   ; None         ; 18.392 ns  ; vga_vl:inst|hcnt[5]  ; VGA_RGB[1] ; clk        ;
; N/A   ; None         ; 18.369 ns  ; vga_vl:inst|hcnt[5]  ; VGA_RGB[2] ; clk        ;
; N/A   ; None         ; 18.157 ns  ; vga_vl:inst|hcnt[3]  ; VGA_RGB[0] ; clk        ;
; N/A   ; None         ; 18.148 ns  ; vga_vl:inst|hcnt[6]  ; VGA_RGB[0] ; clk        ;
; N/A   ; None         ; 18.002 ns  ; vga_vl:inst|hcnt[3]  ; VGA_RGB[1] ; clk        ;
; N/A   ; None         ; 17.993 ns  ; vga_vl:inst|hcnt[6]  ; VGA_RGB[1] ; clk        ;
; N/A   ; None         ; 17.979 ns  ; vga_vl:inst|hcnt[3]  ; VGA_RGB[2] ; clk        ;
; N/A   ; None         ; 17.970 ns  ; vga_vl:inst|hcnt[6]  ; VGA_RGB[2] ; clk        ;
; N/A   ; None         ; 17.969 ns  ; vga_vl:inst|hcnt[2]  ; VGA_RGB[0] ; clk        ;
; N/A   ; None         ; 17.814 ns  ; vga_vl:inst|hcnt[2]  ; VGA_RGB[1] ; clk        ;
; N/A   ; None         ; 17.791 ns  ; vga_vl:inst|hcnt[2]  ; VGA_RGB[2] ; clk        ;
; N/A   ; None         ; 17.764 ns  ; vga_vl:inst|hcnt[4]  ; VGA_RGB[1] ; clk        ;
; N/A   ; None         ; 17.741 ns  ; vga_vl:inst|hcnt[4]  ; VGA_RGB[2] ; clk        ;
; N/A   ; None         ; 17.577 ns  ; vga_vl:inst|hcnt[8]  ; VGA_RGB[1] ; clk        ;
; N/A   ; None         ; 17.554 ns  ; vga_vl:inst|hcnt[8]  ; VGA_RGB[2] ; clk        ;
; N/A   ; None         ; 17.430 ns  ; vga_vl:inst|hcnt[8]  ; VGA_RGB[0] ; clk        ;
; N/A   ; None         ; 17.401 ns  ; vga_vl:inst|hcnt[4]  ; VGA_RGB[0] ; clk        ;
; N/A   ; None         ; 17.397 ns  ; vga_vl:inst|vsync    ; VGA_VS     ; clk        ;
; N/A   ; None         ; 16.950 ns  ; vga_vl:inst|enable   ; VGA_RGB[0] ; clk        ;
; N/A   ; None         ; 16.788 ns  ; vga_vl:inst|hcnt[10] ; VGA_RGB[0] ; clk        ;
; N/A   ; None         ; 16.736 ns  ; vga_vl:inst|hcnt[9]  ; VGA_RGB[2] ; clk        ;
; N/A   ; None         ; 16.708 ns  ; vga_vl:inst|hcnt[10] ; VGA_RGB[2] ; clk        ;
; N/A   ; None         ; 16.679 ns  ; vga_vl:inst|hcnt[9]  ; VGA_RGB[0] ; clk        ;
; N/A   ; None         ; 16.322 ns  ; vga_vl:inst|hcnt[9]  ; VGA_RGB[1] ; clk        ;
; N/A   ; None         ; 16.294 ns  ; vga_vl:inst|hcnt[10] ; VGA_RGB[1] ; clk        ;
; N/A   ; None         ; 16.134 ns  ; vga_vl:inst|enable   ; VGA_RGB[2] ; clk        ;
; N/A   ; None         ; 14.951 ns  ; vga_vl:inst|enable   ; VGA_RGB[1] ; clk        ;
; N/A   ; None         ; 12.658 ns  ; vga_vl:inst|hsyncint ; VGA_HS     ; clk        ;
+-------+--------------+------------+----------------------+------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Thu Feb 16 16:24:06 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ColorBar -c ColorBar
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "vga_vl:inst|hsyncint" as buffer
Info: Clock "clk" has Internal fmax of 45.29 MHz between source register "vga_vl:inst|vcnt[7]" and destination register "vga_vl:inst|enable" (period= 22.08 ns)
    Info: + Longest register to register delay is 5.099 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y6_N2; Fanout = 5; REG Node = 'vga_vl:inst|vcnt[7]'
        Info: 2: + IC(0.943 ns) + CELL(0.740 ns) = 1.683 ns; Loc. = LC_X7_Y6_N9; Fanout = 2; COMB Node = 'vga_vl:inst|always4~151'
        Info: 3: + IC(1.101 ns) + CELL(0.914 ns) = 3.698 ns; Loc. = LC_X8_Y6_N2; Fanout = 1; COMB Node = 'vga_vl:inst|always4~152'
        Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 4.203 ns; Loc. = LC_X8_Y6_N3; Fanout = 1; COMB Node = 'vga_vl:inst|always4~153'
        Info: 5: + IC(0.305 ns) + CELL(0.591 ns) = 5.099 ns; Loc. = LC_X8_Y6_N4; Fanout = 5; REG Node = 'vga_vl:inst|enable'
        Info: Total cell delay = 2.445 ns ( 47.95 % )
        Info: Total interconnect delay = 2.654 ns ( 52.05 % )
    Info: - Smallest clock skew is -5.232 ns
        Info: + Shortest clock path from clock "clk" to destination register is 6.732 ns
            Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 13; CLK Node = 'clk'
            Info: 2: + IC(4.682 ns) + CELL(0.918 ns) = 6.732 ns; Loc. = LC_X8_Y6_N4; Fanout = 5; REG Node = 'vga_vl:inst|enable'
            Info: Total cell delay = 2.050 ns ( 30.45 % )
            Info: Total interconnect delay = 4.682 ns ( 69.55 % )
        Info: - Longest clock path from clock "clk" to source register is 11.964 ns
            Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 13; CLK Node = 'clk'
            Info: 2: + IC(4.682 ns) + CELL(1.294 ns) = 7.108 ns; Loc. = LC_X10_Y7_N4; Fanout = 13; REG Node = 'vga_vl:inst|hsyncint'
            Info: 3: + IC(3.938 ns) + CELL(0.918 ns) = 11.964 ns; Loc. = LC_X7_Y6_N2; Fanout = 5; REG Node = 'vga_vl:inst|vcnt[7]'
            Info: Total cell delay = 3.344 ns ( 27.95 % )
            Info: Total interconnect delay = 8.620 ns ( 72.05 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: tco from clock "clk" to destination pin "VGA_RGB[0]" through register "vga_vl:inst|hcnt[7]" is