colorbar.map.rpt

基于EPM1270的VGA显示器接口源码Verilog

+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name   ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------+
; |ColorBar                  ; 65 (0)      ; 25           ; 0          ; 7    ; 0            ; 40 (0)       ; 0 (0)             ; 25 (0)           ; 22 (0)          ; |ColorBar             ;
;    |vga_vl:inst|           ; 65 (65)     ; 25           ; 0          ; 0    ; 0            ; 40 (40)      ; 0 (0)             ; 25 (25)          ; 22 (22)         ; |ColorBar|vga_vl:inst ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 25    ;
; Number of registers using Synchronous Clear  ; 22    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 25    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; vga_vl:inst|hsyncint                   ; 13      ;
; vga_vl:inst|vsync                      ; 1       ;
; Total number of inverted registers = 2 ;         ;
+----------------------------------------+---------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
; 7:1                ; 2 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |ColorBar|vga_vl:inst|pixel[1] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+


+-----------------------------------------------------------------+
; Parameter Settings for User Entity Instance: vga_vl:inst        ;
+----------------+--------------------------------------+---------+
; Parameter Name ; Value                                ; Type    ;
+----------------+--------------------------------------+---------+
; H_PIXELS       ; 32'b00000000000000000000001100100110 ; Untyped ;
; H_FRONTPORCH   ; 32'b00000000000000000000000000100101 ; Untyped ;
; H_SYNCTIME     ; 32'b00000000000000000000000010000000 ; Untyped ;
; H_BACKPORCH    ; 32'b00000000000000000000000001010101 ; Untyped ;
; H_SYNCSTART    ; 32'b00000000000000000000001101001011 ; Untyped ;
; H_SYNCEND      ; 32'b00000000000000000000001111001011 ; Untyped ;
; H_PERIOD       ; 32'b00000000000000000000010000100000 ; Untyped ;
; V_LINES        ; 32'b00000000000000000000001001011100 ; Untyped ;
; V_FRONTPORCH   ; -1                                   ; Untyped ;
; V_SYNCTIME     ; 32'b00000000000000000000000000000100 ; Untyped ;
; V_BACKPORCH    ; 32'b00000000000000000000000000010101 ; Untyped ;
; V_SYNCSTART    ; 32'b00000000000000000000001001011011 ; Untyped ;
; V_SYNCEND      ; 32'b00000000000000000000001001011111 ; Untyped ;
; V_PERIOD       ; 32'b00000000000000000000001001110100 ; Untyped ;
+----------------+--------------------------------------+---------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/vga/Proj/ColorBar.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Thu Feb 16 16:23:56 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ColorBar -c ColorBar
Info: Found 1 design units, including 1 entities, in source file ../src/vga_vl.v
    Info: Found entity 1: vga_vl
Info: Found 1 design units, including 1 entities, in source file ../Src/ColorBar.bdf
    Info: Found entity 1: ColorBar
Info: Elaborating entity "ColorBar" for the top level hierarchy
Warning: Can't find a definition for parameter H_PIXELS -- assuming 32'b00000000000000000000001100100110 was intended to be a quoted string
Warning: Can't find a definition for parameter H_FRONTPORCH -- assuming 32'b00000000000000000000000000100101 was intended to be a quoted string
Warning: Can't find a definition for parameter H_SYNCTIME -- assuming 32'b00000000000000000000000010000000 was intended to be a quoted string
Warning: Can't find a definition for parameter H_BACKPORCH -- assuming 32'b00000000000000000000000001010101 was intended to be a quoted string
Warning: Can't find a definition for parameter H_SYNCSTART -- assuming 32'b00000000000000000000001101001011 was intended to be a quoted string
Warning: Can't find a definition for parameter H_SYNCEND -- assuming 32'b00000000000000000000001111001011 was intended to be a quoted string
Warning: Can't find a definition for parameter H_PERIOD -- assuming 32'b00000000000000000000010000100000 was intended to be a quoted string
Warning: Can't find a definition for parameter V_LINES -- assuming 32'b00000000000000000000001001011100 was intended to be a quoted string
Warning: Can't find a definition for parameter V_SYNCTIME -- assuming 32'b00000000000000000000000000000100 was intended to be a quoted string
Warning: Can't find a definition for parameter V_BACKPORCH -- assuming 32'b00000000000000000000000000010101 was intended to be a quoted string
Warning: Can't find a definition for parameter V_SYNCSTART -- assuming 32'b00000000000000000000001001011011 was intended to be a quoted string
Warning: Can't find a definition for parameter V_SYNCEND -- assuming 32'b00000000000000000000001001011111 was intended to be a quoted string
Warning: Can't find a definition for parameter V_PERIOD -- assuming 32'b00000000000000000000001001110100 was intended to be a quoted string
Info: Elaborating entity "vga_vl" for hierarchy "vga_vl:inst"
Warning: Verilog HDL assignment warning at vga_vl.v(96): truncated value with size 32 to match size of target (11)
Warning: Verilog HDL assignment warning at vga_vl.v(98): truncated value with size 32 to match size of target (11)
Warning: Verilog HDL assignment warning at vga_vl.v(100): truncated value with size 32 to match size of target (11)
Warning: Verilog HDL assignment warning at vga_vl.v(105): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at vga_vl.v(107): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at vga_vl.v(109): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at vga_vl.v(117): truncated value with size 32 to match size of target (11)
Warning: Verilog HDL assignment warning at vga_vl.v(119): truncated value with size 32 to match size of target (11)
Warning: Verilog HDL assignment warning at vga_vl.v(121): truncated value with size 32 to match size of target (11)
Warning: Verilog HDL assignment warning at vga_vl.v(126): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at vga_vl.v(128): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at vga_vl.v(130): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at vga_vl.v(135): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at vga_vl.v(137): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at vga_vl.v(139): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at vga_vl.v(144): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at vga_vl.v(149): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at vga_vl.v(152): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at vga_vl.v(155): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at vga_vl.v(158): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at vga_vl.v(161): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at vga_vl.v(164): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at vga_vl.v(167): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at vga_vl.v(169): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at vga_vl.v(174): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at vga_vl.v(177): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at vga_vl.v(180): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at vga_vl.v(183): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at vga_vl.v(186): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at vga_vl.v(189): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at vga_vl.v(192): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at vga_vl.v(194): truncated value with size 32 to match size of target (3)
Info: Registers with preset signals will power-up high
Info: Implemented 72 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 5 output pins
    Info: Implemented 65 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 45 warnings
    Info: Processing ended: Thu Feb 16 16:23:58 2006
    Info: Elapsed time: 00:00:02