📄 ps2tolcd.map.qmsg

📁 基于EPM1270的PS2键盘鼠标驱动源码Verilog
💻 QMSG
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{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2_keyboard.v(514) " "Warning: Verilog HDL assignment warning at ps2_keyboard.v(514): truncated value with size 32 to match size of target (1)" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 514 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2_keyboard.v(522) " "Warning: Verilog HDL assignment warning at ps2_keyboard.v(522): truncated value with size 32 to match size of target (1)" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 522 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2_keyboard.v(524) " "Warning: Verilog HDL assignment warning at ps2_keyboard.v(524): truncated value with size 32 to match size of target (1)" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 524 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2_keyboard.v(526) " "Warning: Verilog HDL assignment warning at ps2_keyboard.v(526): truncated value with size 32 to match size of target (1)" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 526 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2_keyboard.v(531) " "Warning: Verilog HDL assignment warning at ps2_keyboard.v(531): truncated value with size 32 to match size of target (1)" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 531 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2_keyboard.v(533) " "Warning: Verilog HDL assignment warning at ps2_keyboard.v(533): truncated value with size 32 to match size of target (1)" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 533 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2_keyboard.v(535) " "Warning: Verilog HDL assignment warning at ps2_keyboard.v(535): truncated value with size 32 to match size of target (1)" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 535 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2_keyboard.v(545) " "Warning: Verilog HDL assignment warning at ps2_keyboard.v(545): truncated value with size 32 to match size of target (1)" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 545 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2_keyboard.v(546) " "Warning: Verilog HDL assignment warning at ps2_keyboard.v(546): truncated value with size 32 to match size of target (1)" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 546 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 ps2_keyboard.v(547) " "Warning: Verilog HDL assignment warning at ps2_keyboard.v(547): truncated value with size 32 to match size of target (8)" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 547 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 ps2_keyboard.v(548) " "Warning: Verilog HDL assignment warning at ps2_keyboard.v(548): truncated value with size 32 to match size of target (8)" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 548 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div_256 div_256:inst1 " "Info: Elaborating entity \"div_256\" for hierarchy \"div_256:inst1\"" {  } { { "ps2tolcd.bdf" "inst1" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 184 104 200 280 "inst1" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 div_256.v(13) " "Warning: Verilog HDL assignment warning at div_256.v(13): truncated value with size 32 to match size of target (7)" {  } { { "../SRC/div_256.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/div_256.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 div_256.v(16) " "Warning: Verilog HDL assignment warning at div_256.v(16): truncated value with size 32 to match size of target (7)" {  } { { "../SRC/div_256.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/div_256.v" 16 0 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ps2_keyboard_interface:inst3\|rx_ascii\[7\] data_in GND " "Warning: Reduced register \"ps2_keyboard_interface:inst3\|rx_ascii\[7\]\" with stuck data_in port to stuck value GND" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 191 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state 15 0 " "Info: State machine \"\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state\" contains 15 states and 0 state bits" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state " "Info: Selected Auto state machine encoding method for state machine \"\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state " "Info: Encoding result for state machine \"\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "15 " "Info: Completed encoding using 15 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ps2_keyboard_interface:inst3\|m1_state.m1_tx_done_recovery " "Info: Encoded state bit \"ps2_keyboard_interface:inst3\|m1_state.m1_tx_done_recovery\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ps2_keyboard_interface:inst3\|m1_state.m1_tx_reset_timer " "Info: Encoded state bit \"ps2_keyboard_interface:inst3\|m1_state.m1_tx_reset_timer\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ps2_keyboard_interface:inst3\|m1_state.m1_rx_falling_edge_marker " "Info: Encoded state bit \"ps2_keyboard_interface:inst3\|m1_state.m1_rx_falling_edge_marker\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ps2_keyboard_interface:inst3\|m1_state.m1_rx_clk_l " "Info: Encoded state bit \"ps2_keyboard_interface:inst3\|m1_state.m1_rx_clk_l\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ps2_keyboard_interface:inst3\|m1_state.m1_rx_rising_edge_marker " "Info: Encoded state bit \"ps2_keyboard_interface:inst3\|m1_state.m1_rx_rising_edge_marker\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ps2_keyboard_interface:inst3\|m1_state.m1_tx_force_clk_l " "Info: Encoded state bit \"ps2_keyboard_interface:inst3\|m1_state.m1_tx_force_clk_l\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ps2_keyboard_interface:inst3\|m1_state.m1_tx_first_wait_clk_h " "Info: Encoded state bit \"ps2_keyboard_interface:inst3\|m1_state.m1_tx_first_wait_clk_h\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ps2_keyboard_interface:inst3\|m1_state.m1_tx_clk_l " "Info: Encoded state bit \"ps2_keyboard_interface:inst3\|m1_state.m1_tx_clk_l\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ps2_keyboard_interface:inst3\|m1_state.m1_tx_first_wait_clk_l " "Info: Encoded state bit \"ps2_keyboard_interface:inst3\|m1_state.m1_tx_first_wait_clk_l\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ps2_keyboard_interface:inst3\|m1_state.m1_tx_wait_clk_h " "Info: Encoded state bit \"ps2_keyboard_interface:inst3\|m1_state.m1_tx_wait_clk_h\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ps2_keyboard_interface:inst3\|m1_state.m1_tx_rising_edge_marker " "Info: Encoded state bit \"ps2_keyboard_interface:inst3\|m1_state.m1_tx_rising_edge_marker\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ps2_keyboard_interface:inst3\|m1_state.m1_tx_clk_h " "Info: Encoded state bit \"ps2_keyboard_interface:inst3\|m1_state.m1_tx_clk_h\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ps2_keyboard_interface:inst3\|m1_state.m1_tx_wait_keyboard_ack " "Info: Encoded state bit \"ps2_keyboard_interface:inst3\|m1_state.m1_tx_wait_keyboard_ack\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ps2_keyboard_interface:inst3\|m1_state.m1_tx_error_no_keyboard_ack " "Info: Encoded state bit \"ps2_keyboard_interface:inst3\|m1_state.m1_tx_error_no_keyboard_ack\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ps2_keyboard_interface:inst3\|m1_state.m1_rx_clk_h " "Info: Encoded state bit \"ps2_keyboard_interface:inst3\|m1_state.m1_rx_clk_h\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_rx_clk_h 000000000000000 " "Info: State \"\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_rx_clk_h\" uses code string \"000000000000000\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_tx_error_no_keyboard_ack 000000000000011 " "Info: State \"\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_tx_error_no_keyboard_ack\" uses code string \"000000000000011\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_tx_wait_keyboard_ack 000000000000101 " "Info: State \"\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_tx_wait_keyboard_ack\" uses code string \"000000000000101\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_tx_clk_h 000000000001001 " "Info: State \"\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_tx_clk_h\" uses code string \"000000000001001\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_tx_rising_edge_marker 000000000010001 " "Info: State \"\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_tx_rising_edge_marker\" uses code string \"000000000010001\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_tx_wait_clk_h 000000000100001 " "Info: State \"\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_tx_wait_clk_h\" uses code string \"000000000100001\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_tx_first_wait_clk_l 000000001000001 " "Info: State \"\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_tx_first_wait_clk_l\" uses code string \"000000001000001\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_tx_clk_l 000000010000001 " "Info: State \"\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_tx_clk_l\" uses code string \"000000010000001\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_tx_first_wait_clk_h 000000100000001 " "Info: State \"\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_tx_first_wait_clk_h\" uses code string \"000000100000001\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_tx_force_clk_l 000001000000001 " "Info: State \"\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_tx_force_clk_l\" uses code string \"000001000000001\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_rx_rising_edge_marker 000010000000001 " "Info: State \"\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_rx_rising_edge_marker\" uses code string \"000010000000001\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_rx_clk_l 000100000000001 " "Info: State \"\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_rx_clk_l\" uses code string \"000100000000001\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_rx_falling_edge_marker 001000000000001 " "Info: State \"\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_rx_falling_edge_marker\" uses code string \"001000000000001\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_tx_reset_timer 010000000000001 " "Info: State \"\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_tx_reset_timer\" uses code string \"010000000000001\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_tx_done_recovery 100000000000001 " "Info: State \"\|ps2tolcd\|ps2_keyboard_interface:inst3\|m1_state.m1_tx_done_recovery\" uses code string \"100000000000001\"" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0}  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ps2_keyboard_interface:inst3\|m1_state.m1_tx_force_clk_l data_in GND " "Warning: Reduced register \"ps2_keyboard_interface:inst3\|m1_state.m1_tx_force_clk_l\" with stuck data_in port to stuck value GND" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ps2_keyboard_interface:inst3\|m1_state.m1_tx_first_wait_clk_h data_in GND " "Warning: Reduced register \"ps2_keyboard_interface:inst3\|m1_state.m1_tx_first_wait_clk_h\" with stuck data_in port to stuck value GND" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ps2_keyboard_interface:inst3\|m1_state.m1_tx_first_wait_clk_l data_in GND " "Warning: Reduced register \"ps2_keyboard_interface:inst3\|m1_state.m1_tx_first_wait_clk_l\" with stuck data_in port to stuck value GND" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 229 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "led\[7\] GND " "Warning: Pin \"led\[7\]\" stuck at GND" {  } { { "ps2tolcd.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 360 624 800 376 "led\[7..0\]" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "278 " "Info: Implemented 278 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "2 " "Info: Implemented 2 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "266 " "Info: Implemented 266 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 58 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 58 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 15:13:51 2006 " "Info: Processing ended: Sat Feb 18 15:13:51 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Info: Elapsed time: 00:00:18" {  } {  } 0}  } {  } 0}
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