ps2tolcd.fit.qmsg

基于EPM1270的PS2键盘鼠标驱动源码Verilog

{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "" "Info: Finished moving registers into LUTs" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "16.042 ns register register " "Info: Estimated most critical path is register to register delay of 16.042 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ps2_keyboard_interface:inst3\|left_shift_key 1 REG LAB_X8_Y6 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X8_Y6; Fanout = 15; REG Node = 'ps2_keyboard_interface:inst3\|left_shift_key'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { ps2_keyboard_interface:inst3|left_shift_key } "NODE_NAME" } "" } } { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 239 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.446 ns) + CELL(0.914 ns) 1.360 ns ps2_keyboard_interface:inst3\|rx_shift_key_on~0 2 COMB LAB_X8_Y6 30 " "Info: 2: + IC(0.446 ns) + CELL(0.914 ns) = 1.360 ns; Loc. = LAB_X8_Y6; Fanout = 30; COMB Node = 'ps2_keyboard_interface:inst3\|rx_shift_key_on~0'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.360 ns" { ps2_keyboard_interface:inst3|left_shift_key ps2_keyboard_interface:inst3|rx_shift_key_on~0 } "NODE_NAME" } "" } } { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 189 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.902 ns) + CELL(0.511 ns) 3.773 ns ps2_keyboard_interface:inst3\|reduce_nor~4901 3 COMB LAB_X9_Y7 5 " "Info: 3: + IC(1.902 ns) + CELL(0.511 ns) = 3.773 ns; Loc. = LAB_X9_Y7; Fanout = 5; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_nor~4901'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "2.413 ns" { ps2_keyboard_interface:inst3|rx_shift_key_on~0 ps2_keyboard_interface:inst3|reduce_nor~4901 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.673 ns) + CELL(0.740 ns) 6.186 ns ps2_keyboard_interface:inst3\|reduce_nor~4951 4 COMB LAB_X9_Y8 1 " "Info: 4: + IC(1.673 ns) + CELL(0.740 ns) = 6.186 ns; Loc. = LAB_X9_Y8; Fanout = 1; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_nor~4951'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "2.413 ns" { ps2_keyboard_interface:inst3|reduce_nor~4901 ps2_keyboard_interface:inst3|reduce_nor~4951 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.672 ns) + CELL(0.511 ns) 7.369 ns ps2_keyboard_interface:inst3\|reduce_nor~4952 5 COMB LAB_X9_Y8 1 " "Info: 5: + IC(0.672 ns) + CELL(0.511 ns) = 7.369 ns; Loc. = LAB_X9_Y8; Fanout = 1; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_nor~4952'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.183 ns" { ps2_keyboard_interface:inst3|reduce_nor~4951 ps2_keyboard_interface:inst3|reduce_nor~4952 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.702 ns) + CELL(0.740 ns) 9.811 ns ps2_keyboard_interface:inst3\|reduce_nor~4958 6 COMB LAB_X8_Y6 3 " "Info: 6: + IC(1.702 ns) + CELL(0.740 ns) = 9.811 ns; Loc. = LAB_X8_Y6; Fanout = 3; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_nor~4958'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "2.442 ns" { ps2_keyboard_interface:inst3|reduce_nor~4952 ps2_keyboard_interface:inst3|reduce_nor~4958 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.213 ns) + CELL(0.200 ns) 12.224 ns ps2_keyboard_interface:inst3\|reduce_nor~104 7 COMB LAB_X7_Y7 2 " "Info: 7: + IC(2.213 ns) + CELL(0.200 ns) = 12.224 ns; Loc. = LAB_X7_Y7; Fanout = 2; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_nor~104'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "2.413 ns" { ps2_keyboard_interface:inst3|reduce_nor~4958 ps2_keyboard_interface:inst3|reduce_nor~104 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.269 ns) + CELL(0.914 ns) 13.407 ns ps2_keyboard_interface:inst3\|reduce_or~1287 8 COMB LAB_X7_Y7 2 " "Info: 8: + IC(0.269 ns) + CELL(0.914 ns) = 13.407 ns; Loc. = LAB_X7_Y7; Fanout = 2; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_or~1287'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.183 ns" { ps2_keyboard_interface:inst3|reduce_nor~104 ps2_keyboard_interface:inst3|reduce_or~1287 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.672 ns) + CELL(0.511 ns) 14.590 ns ps2_keyboard_interface:inst3\|reduce_or~14 9 COMB LAB_X7_Y7 1 " "Info: 9: + IC(0.672 ns) + CELL(0.511 ns) = 14.590 ns; Loc. = LAB_X7_Y7; Fanout = 1; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_or~14'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.183 ns" { ps2_keyboard_interface:inst3|reduce_or~1287 ps2_keyboard_interface:inst3|reduce_or~14 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.269 ns) + CELL(1.183 ns) 16.042 ns ps2_keyboard_interface:inst3\|rx_ascii\[6\] 10 REG LAB_X7_Y7 1 " "Info: 10: + IC(0.269 ns) + CELL(1.183 ns) = 16.042 ns; Loc. = LAB_X7_Y7; Fanout = 1; REG Node = 'ps2_keyboard_interface:inst3\|rx_ascii\[6\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.452 ns" { ps2_keyboard_interface:inst3|reduce_or~14 ps2_keyboard_interface:inst3|rx_ascii[6] } "NODE_NAME" } "" } } { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 191 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.224 ns 38.80 % " "Info: Total cell delay = 6.224 ns ( 38.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.818 ns 61.20 % " "Info: Total interconnect delay = 9.818 ns ( 61.20 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "16.042 ns" { ps2_keyboard_interface:inst3|left_shift_key ps2_keyboard_interface:inst3|rx_shift_key_on~0 ps2_keyboard_interface:inst3|reduce_nor~4901 ps2_keyboard_interface:inst3|reduce_nor~4951 ps2_keyboard_interface:inst3|reduce_nor~4952 ps2_keyboard_interface:inst3|reduce_nor~4958 ps2_keyboard_interface:inst3|reduce_nor~104 ps2_keyboard_interface:inst3|reduce_or~1287 ps2_keyboard_interface:inst3|reduce_or~14 ps2_keyboard_interface:inst3|rx_ascii[6] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:04 " "Info: Fitter placement operations ending: elapsed time is 00:00:04" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "6 6 " "Info: Average interconnect usage is 6% of the available device resources. Peak interconnect usage is 6%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:06 " "Info: Fitter routing operations ending: elapsed time is 00:00:06" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "Info: Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and/or routability requirements required full optimization" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "1 " "Warning: The following 1 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ps2_clk a permanently enabled " "Info: Pin ps2_clk has a permanently enabled output enable" {  } { { "ps2tolcd.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 264 608 784 280 "ps2_clk" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ps2_clk" } } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { ps2_clk } "NODE_NAME" } "" } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.fld" "" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.fld" "" "" { ps2_clk } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: The following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "ps2_keyboard_interface:inst3\|ps2_data_hi_z~29 " "Info: The following pins have the same output enable: ps2_keyboard_interface:inst3\|ps2_data_hi_z~29" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ps2_data LVTTL " "Info: Type bidirectional pin ps2_data uses the LVTTL I/O standard" {  } { { "ps2tolcd.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 280 608 784 296 "ps2_data" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ps2_data" } } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { ps2_data } "NODE_NAME" } "" } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.fld" "" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.fld" "" "" { ps2_data } "NODE_NAME" } }  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 15:14:13 2006 " "Info: Processing ended: Sat Feb 18 15:14:13 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Info: Elapsed time: 00:00:18" {  } {  } 0}  } {  } 0}