⭐ 欢迎来到虫虫下载站！ | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站
📤 上传资源

📄 ps2tolcd.tan.qmsg

📁 基于EPM1270的PS2键盘鼠标驱动源码Verilog
💻 QMSG
📖 第 1 页 / 共 4 页
字号:
🔍
1234 
{ "Info" "ITDB_TSU_RESULT" "div_256:inst1\|clk reset mclk -1.016 ns register " "Info: tsu for register \"div_256:inst1\|clk\" (data pin = \"reset\", clock pin = \"mclk\") is -1.016 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.903 ns + Longest pin register " "Info: + Longest pin to register delay is 5.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns reset 1 PIN PIN_110 42 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_110; Fanout = 42; PIN Node = 'reset'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { reset } "NODE_NAME" } "" } } { "ps2tolcd.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 280 -176 -8 296 "reset" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.528 ns) + CELL(1.243 ns) 5.903 ns div_256:inst1\|clk 2 REG LC_X12_Y3_N7 58 " "Info: 2: + IC(3.528 ns) + CELL(1.243 ns) = 5.903 ns; Loc. = LC_X12_Y3_N7; Fanout = 58; REG Node = 'div_256:inst1\|clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "4.771 ns" { reset div_256:inst1|clk } "NODE_NAME" } "" } } { "../SRC/div_256.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/div_256.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.375 ns 40.23 % " "Info: Total cell delay = 2.375 ns ( 40.23 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.528 ns 59.77 % " "Info: Total interconnect delay = 3.528 ns ( 59.77 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "5.903 ns" { reset div_256:inst1|clk } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.903 ns" { reset reset~combout div_256:inst1|clk } { 0.000ns 0.000ns 3.528ns } { 0.000ns 1.132ns 1.243ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "../SRC/div_256.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/div_256.v" 5 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 7.252 ns - Shortest register " "Info: - Shortest clock path from clock \"mclk\" to destination register is 7.252 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns mclk 1 CLK PIN_127 8 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 8; CLK Node = 'mclk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { mclk } "NODE_NAME" } "" } } { "ps2tolcd.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 208 -176 -8 224 "mclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.202 ns) + CELL(0.918 ns) 7.252 ns div_256:inst1\|clk 2 REG LC_X12_Y3_N7 58 " "Info: 2: + IC(5.202 ns) + CELL(0.918 ns) = 7.252 ns; Loc. = LC_X12_Y3_N7; Fanout = 58; REG Node = 'div_256:inst1\|clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "6.120 ns" { mclk div_256:inst1|clk } "NODE_NAME" } "" } } { "../SRC/div_256.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/div_256.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 28.27 % " "Info: Total cell delay = 2.050 ns ( 28.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.202 ns 71.73 % " "Info: Total interconnect delay = 5.202 ns ( 71.73 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "7.252 ns" { mclk div_256:inst1|clk } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.252 ns" { mclk mclk~combout div_256:inst1|clk } { 0.000ns 0.000ns 5.202ns } { 0.000ns 1.132ns 0.918ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "5.903 ns" { reset div_256:inst1|clk } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.903 ns" { reset reset~combout div_256:inst1|clk } { 0.000ns 0.000ns 3.528ns } { 0.000ns 1.132ns 1.243ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "7.252 ns" { mclk div_256:inst1|clk } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.252 ns" { mclk mclk~combout div_256:inst1|clk } { 0.000ns 0.000ns 5.202ns } { 0.000ns 1.132ns 0.918ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "mclk led\[2\] ps2_keyboard_interface:inst3\|rx_ascii\[2\] 16.346 ns register " "Info: tco from clock \"mclk\" to destination pin \"led\[2\]\" through register \"ps2_keyboard_interface:inst3\|rx_ascii\[2\]\" is 16.346 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk source 10.973 ns + Longest register " "Info: + Longest clock path from clock \"mclk\" to source register is 10.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns mclk 1 CLK PIN_127 8 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 8; CLK Node = 'mclk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { mclk } "NODE_NAME" } "" } } { "ps2tolcd.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 208 -176 -8 224 "mclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.202 ns) + CELL(1.294 ns) 7.628 ns div_256:inst1\|clk 2 REG LC_X12_Y3_N7 58 " "Info: 2: + IC(5.202 ns) + CELL(1.294 ns) = 7.628 ns; Loc. = LC_X12_Y3_N7; Fanout = 58; REG Node = 'div_256:inst1\|clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "6.496 ns" { mclk div_256:inst1|clk } "NODE_NAME" } "" } } { "../SRC/div_256.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/div_256.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.427 ns) + CELL(0.918 ns) 10.973 ns ps2_keyboard_interface:inst3\|rx_ascii\[2\] 3 REG LC_X7_Y7_N9 1 " "Info: 3: + IC(2.427 ns) + CELL(0.918 ns) = 10.973 ns; Loc. = LC_X7_Y7_N9; Fanout = 1; REG Node = 'ps2_keyboard_interface:inst3\|rx_ascii\[2\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "3.345 ns" { div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[2] } "NODE_NAME" } "" } } { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 191 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns 30.47 % " "Info: Total cell delay = 3.344 ns ( 30.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.629 ns 69.53 % " "Info: Total interconnect delay = 7.629 ns ( 69.53 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "10.973 ns" { mclk div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.973 ns" { mclk mclk~combout div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[2] } { 0.000ns 0.000ns 5.202ns 2.427ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 191 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.997 ns + Longest register pin " "Info: + Longest register to pin delay is 4.997 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ps2_keyboard_interface:inst3\|rx_ascii\[2\] 1 REG LC_X7_Y7_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y7_N9; Fanout = 1; REG Node = 'ps2_keyboard_interface:inst3\|rx_ascii\[2\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { ps2_keyboard_interface:inst3|rx_ascii[2] } "NODE_NAME" } "" } } { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 191 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.675 ns) + CELL(2.322 ns) 4.997 ns led\[2\] 2 PIN PIN_38 0 " "Info: 2: + IC(2.675 ns) + CELL(2.322 ns) = 4.997 ns; Loc. = PIN_38; Fanout = 0; PIN Node = 'led\[2\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "4.997 ns" { ps2_keyboard_interface:inst3|rx_ascii[2] led[2] } "NODE_NAME" } "" } } { "ps2tolcd.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 360 624 800 376 "led\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns 46.47 % " "Info: Total cell delay = 2.322 ns ( 46.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.675 ns 53.53 % " "Info: Total interconnect delay = 2.675 ns ( 53.53 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "4.997 ns" { ps2_keyboard_interface:inst3|rx_ascii[2] led[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.997 ns" { ps2_keyboard_interface:inst3|rx_ascii[2] led[2] } { 0.000ns 2.675ns } { 0.000ns 2.322ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "10.973 ns" { mclk div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.973 ns" { mclk mclk~combout div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[2] } { 0.000ns 0.000ns 5.202ns 2.427ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "4.997 ns" { ps2_keyboard_interface:inst3|rx_ascii[2] led[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.997 ns" { ps2_keyboard_interface:inst3|rx_ascii[2] led[2] } { 0.000ns 2.675ns } { 0.000ns 2.322ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "ps2_keyboard_interface:inst3\|q\[0\] reset mclk 6.448 ns register " "Info: th for register \"ps2_keyboard_interface:inst3\|q\[0\]\" (data pin = \"reset\", clock pin = \"mclk\") is 6.448 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 10.973 ns + Longest register " "Info: + Longest clock path from clock \"mclk\" to destination register is 10.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns mclk 1 CLK PIN_127 8 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 8; CLK Node = 'mclk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { mclk } "NODE_NAME" } "" } } { "ps2tolcd.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 208 -176 -8 224 "mclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.202 ns) + CELL(1.294 ns) 7.628 ns div_256:inst1\|clk 2 REG LC_X12_Y3_N7 58 " "Info: 2: + IC(5.202 ns) + CELL(1.294 ns) = 7.628 ns; Loc. = LC_X12_Y3_N7; Fanout = 58; REG Node = 'div_256:inst1\|clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "6.496 ns" { mclk div_256:inst1|clk } "NODE_NAME" } "" } } { "../SRC/div_256.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/div_256.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.427 ns) + CELL(0.918 ns) 10.973 ns ps2_keyboard_interface:inst3\|q\[0\] 3 REG LC_X16_Y5_N5 1 " "Info: 3: + IC(2.427 ns) + CELL(0.918 ns) = 10.973 ns; Loc. = LC_X16_Y5_N5; Fanout = 1; REG Node = 'ps2_keyboard_interface:inst3\|q\[0\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "3.345 ns" { div_256:inst1|clk ps2_keyboard_interface:inst3|q[0] } "NODE_NAME" } "" } } { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 228 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns 30.47 % " "Info: Total cell delay = 3.344 ns ( 30.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.629 ns 69.53 % " "Info: Total interconnect delay = 7.629 ns ( 69.53 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "10.973 ns" { mclk div_256:inst1|clk ps2_keyboard_interface:inst3|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.973 ns" { mclk mclk~combout div_256:inst1|clk ps2_keyboard_interface:inst3|q[0] } { 0.000ns 0.000ns 5.202ns 2.427ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 228 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.746 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.746 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns reset 1 PIN PIN_110 42 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_110; Fanout = 42; PIN Node = 'reset'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { reset } "NODE_NAME" } "" } } { "ps2tolcd.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 280 -176 -8 296 "reset" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.023 ns) + CELL(0.591 ns) 4.746 ns ps2_keyboard_interface:inst3\|q\[0\] 2 REG LC_X16_Y5_N5 1 " "Info: 2: + IC(3.023 ns) + CELL(0.591 ns) = 4.746 ns; Loc. = LC_X16_Y5_N5; Fanout = 1; REG Node = 'ps2_keyboard_interface:inst3\|q\[0\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "3.614 ns" { reset ps2_keyboard_interface:inst3|q[0] } "NODE_NAME" } "" } } { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 228 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.723 ns 36.30 % " "Info: Total cell delay = 1.723 ns ( 36.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.023 ns 63.70 % " "Info: Total interconnect delay = 3.023 ns ( 63.70 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "4.746 ns" { reset ps2_keyboard_interface:inst3|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.746 ns" { reset reset~combout ps2_keyboard_interface:inst3|q[0] } { 0.000ns 0.000ns 3.023ns } { 0.000ns 1.132ns 0.591ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "10.973 ns" { mclk div_256:inst1|clk ps2_keyboard_interface:inst3|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.973 ns" { mclk mclk~combout div_256:inst1|clk ps2_keyboard_interface:inst3|q[0] } { 0.000ns 0.000ns 5.202ns 2.427ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "4.746 ns" { reset ps2_keyboard_interface:inst3|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.746 ns" { reset reset~combout ps2_keyboard_interface:inst3|q[0] } { 0.000ns 0.000ns 3.023ns } { 0.000ns 1.132ns 0.591ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 15:14:26 2006 " "Info: Processing ended: Sat Feb 18 15:14:26 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0}  } {  } 0}
1234

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -