ps2tolcd.tan.qmsg

基于EPM1270的PS2键盘鼠标驱动源码Verilog

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "mclk " "Info: Assuming node \"mclk\" is an undefined clock" {  } { { "ps2tolcd.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 208 -176 -8 224 "mclk" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "mclk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "div_256:inst1\|clk " "Info: Detected ripple clock \"div_256:inst1\|clk\" as buffer" {  } { { "../SRC/div_256.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/div_256.v" 5 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "div_256:inst1\|clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "mclk register ps2_keyboard_interface:inst3\|q\[2\] register ps2_keyboard_interface:inst3\|rx_ascii\[1\] 63.99 MHz 15.628 ns Internal " "Info: Clock \"mclk\" has Internal fmax of 63.99 MHz between source register \"ps2_keyboard_interface:inst3\|q\[2\]\" and destination register \"ps2_keyboard_interface:inst3\|rx_ascii\[1\]\" (period= 15.628 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.919 ns + Longest register register " "Info: + Longest register to register delay is 14.919 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ps2_keyboard_interface:inst3\|q\[2\] 1 REG LC_X9_Y6_N2 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y6_N2; Fanout = 18; REG Node = 'ps2_keyboard_interface:inst3\|q\[2\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { ps2_keyboard_interface:inst3|q[2] } "NODE_NAME" } "" } } { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 228 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.972 ns) + CELL(0.740 ns) 1.712 ns ps2_keyboard_interface:inst3\|reduce_nor~4904 2 COMB LC_X9_Y6_N5 6 " "Info: 2: + IC(0.972 ns) + CELL(0.740 ns) = 1.712 ns; Loc. = LC_X9_Y6_N5; Fanout = 6; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_nor~4904'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.712 ns" { ps2_keyboard_interface:inst3|q[2] ps2_keyboard_interface:inst3|reduce_nor~4904 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.678 ns) + CELL(0.200 ns) 4.590 ns ps2_keyboard_interface:inst3\|reduce_nor~4932 3 COMB LC_X8_Y9_N6 4 " "Info: 3: + IC(2.678 ns) + CELL(0.200 ns) = 4.590 ns; Loc. = LC_X8_Y9_N6; Fanout = 4; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_nor~4932'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "2.878 ns" { ps2_keyboard_interface:inst3|reduce_nor~4904 ps2_keyboard_interface:inst3|reduce_nor~4932 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.784 ns) + CELL(0.511 ns) 5.885 ns ps2_keyboard_interface:inst3\|reduce_or~1281 4 COMB LC_X8_Y9_N0 1 " "Info: 4: + IC(0.784 ns) + CELL(0.511 ns) = 5.885 ns; Loc. = LC_X8_Y9_N0; Fanout = 1; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_or~1281'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.295 ns" { ps2_keyboard_interface:inst3|reduce_nor~4932 ps2_keyboard_interface:inst3|reduce_or~1281 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.047 ns) + CELL(0.511 ns) 8.443 ns ps2_keyboard_interface:inst3\|reduce_or~1282 5 COMB LC_X8_Y6_N2 2 " "Info: 5: + IC(2.047 ns) + CELL(0.511 ns) = 8.443 ns; Loc. = LC_X8_Y6_N2; Fanout = 2; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_or~1282'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "2.558 ns" { ps2_keyboard_interface:inst3|reduce_or~1281 ps2_keyboard_interface:inst3|reduce_or~1282 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.737 ns) + CELL(0.740 ns) 9.920 ns ps2_keyboard_interface:inst3\|reduce_nor~4958 6 COMB LC_X8_Y6_N4 3 " "Info: 6: + IC(0.737 ns) + CELL(0.740 ns) = 9.920 ns; Loc. = LC_X8_Y6_N4; Fanout = 3; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_nor~4958'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.477 ns" { ps2_keyboard_interface:inst3|reduce_or~1282 ps2_keyboard_interface:inst3|reduce_nor~4958 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.999 ns) + CELL(0.511 ns) 12.430 ns ps2_keyboard_interface:inst3\|reduce_nor~104 7 COMB LC_X7_Y7_N2 2 " "Info: 7: + IC(1.999 ns) + CELL(0.511 ns) = 12.430 ns; Loc. = LC_X7_Y7_N2; Fanout = 2; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_nor~104'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "2.510 ns" { ps2_keyboard_interface:inst3|reduce_nor~4958 ps2_keyboard_interface:inst3|reduce_nor~104 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 12.935 ns ps2_keyboard_interface:inst3\|reduce_or~1287 8 COMB LC_X7_Y7_N3 2 " "Info: 8: + IC(0.305 ns) + CELL(0.200 ns) = 12.935 ns; Loc. = LC_X7_Y7_N3; Fanout = 2; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_or~1287'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "0.505 ns" { ps2_keyboard_interface:inst3|reduce_nor~104 ps2_keyboard_interface:inst3|reduce_or~1287 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.180 ns) + CELL(0.804 ns) 14.919 ns ps2_keyboard_interface:inst3\|rx_ascii\[1\] 9 REG LC_X6_Y7_N3 1 " "Info: 9: + IC(1.180 ns) + CELL(0.804 ns) = 14.919 ns; Loc. = LC_X6_Y7_N3; Fanout = 1; REG Node = 'ps2_keyboard_interface:inst3\|rx_ascii\[1\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.984 ns" { ps2_keyboard_interface:inst3|reduce_or~1287 ps2_keyboard_interface:inst3|rx_ascii[1] } "NODE_NAME" } "" } } { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 191 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.217 ns 28.27 % " "Info: Total cell delay = 4.217 ns ( 28.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.702 ns 71.73 % " "Info: Total interconnect delay = 10.702 ns ( 71.73 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "14.919 ns" { ps2_keyboard_interface:inst3|q[2] ps2_keyboard_interface:inst3|reduce_nor~4904 ps2_keyboard_interface:inst3|reduce_nor~4932 ps2_keyboard_interface:inst3|reduce_or~1281 ps2_keyboard_interface:inst3|reduce_or~1282 ps2_keyboard_interface:inst3|reduce_nor~4958 ps2_keyboard_interface:inst3|reduce_nor~104 ps2_keyboard_interface:inst3|reduce_or~1287 ps2_keyboard_interface:inst3|rx_ascii[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "14.919 ns" { ps2_keyboard_interface:inst3|q[2] ps2_keyboard_interface:inst3|reduce_nor~4904 ps2_keyboard_interface:inst3|reduce_nor~4932 ps2_keyboard_interface:inst3|reduce_or~1281 ps2_keyboard_interface:inst3|reduce_or~1282 ps2_keyboard_interface:inst3|reduce_nor~4958 ps2_keyboard_interface:inst3|reduce_nor~104 ps2_keyboard_interface:inst3|reduce_or~1287 ps2_keyboard_interface:inst3|rx_ascii[1] } { 0.000ns 0.972ns 2.678ns 0.784ns 2.047ns 0.737ns 1.999ns 0.305ns 1.180ns } { 0.000ns 0.740ns 0.200ns 0.511ns 0.511ns 0.740ns 0.511ns 0.200ns 0.804ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 10.973 ns + Shortest register " "Info: + Shortest clock path from clock \"mclk\" to destination register is 10.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns mclk 1 CLK PIN_127 8 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 8; CLK Node = 'mclk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { mclk } "NODE_NAME" } "" } } { "ps2tolcd.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 208 -176 -8 224 "mclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.202 ns) + CELL(1.294 ns) 7.628 ns div_256:inst1\|clk 2 REG LC_X12_Y3_N7 58 " "Info: 2: + IC(5.202 ns) + CELL(1.294 ns) = 7.628 ns; Loc. = LC_X12_Y3_N7; Fanout = 58; REG Node = 'div_256:inst1\|clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "6.496 ns" { mclk div_256:inst1|clk } "NODE_NAME" } "" } } { "../SRC/div_256.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/div_256.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.427 ns) + CELL(0.918 ns) 10.973 ns ps2_keyboard_interface:inst3\|rx_ascii\[1\] 3 REG LC_X6_Y7_N3 1 " "Info: 3: + IC(2.427 ns) + CELL(0.918 ns) = 10.973 ns; Loc. = LC_X6_Y7_N3; Fanout = 1; REG Node = 'ps2_keyboard_interface:inst3\|rx_ascii\[1\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "3.345 ns" { div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[1] } "NODE_NAME" } "" } } { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 191 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns 30.47 % " "Info: Total cell delay = 3.344 ns ( 30.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.629 ns 69.53 % " "Info: Total interconnect delay = 7.629 ns ( 69.53 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "10.973 ns" { mclk div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.973 ns" { mclk mclk~combout div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[1] } { 0.000ns 0.000ns 5.202ns 2.427ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk source 10.973 ns - Longest register " "Info: - Longest clock path from clock \"mclk\" to source register is 10.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns mclk 1 CLK PIN_127 8 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 8; CLK Node = 'mclk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { mclk } "NODE_NAME" } "" } } { "ps2tolcd.bdf" "" { Schematic "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 208 -176 -8 224 "mclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.202 ns) + CELL(1.294 ns) 7.628 ns div_256:inst1\|clk 2 REG LC_X12_Y3_N7 58 " "Info: 2: + IC(5.202 ns) + CELL(1.294 ns) = 7.628 ns; Loc. = LC_X12_Y3_N7; Fanout = 58; REG Node = 'div_256:inst1\|clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "6.496 ns" { mclk div_256:inst1|clk } "NODE_NAME" } "" } } { "../SRC/div_256.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/div_256.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.427 ns) + CELL(0.918 ns) 10.973 ns ps2_keyboard_interface:inst3\|q\[2\] 3 REG LC_X9_Y6_N2 18 " "Info: 3: + IC(2.427 ns) + CELL(0.918 ns) = 10.973 ns; Loc. = LC_X9_Y6_N2; Fanout = 18; REG Node = 'ps2_keyboard_interface:inst3\|q\[2\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "3.345 ns" { div_256:inst1|clk ps2_keyboard_interface:inst3|q[2] } "NODE_NAME" } "" } } { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 228 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns 30.47 % " "Info: Total cell delay = 3.344 ns ( 30.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.629 ns 69.53 % " "Info: Total interconnect delay = 7.629 ns ( 69.53 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "10.973 ns" { mclk div_256:inst1|clk ps2_keyboard_interface:inst3|q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.973 ns" { mclk mclk~combout div_256:inst1|clk ps2_keyboard_interface:inst3|q[2] } { 0.000ns 0.000ns 5.202ns 2.427ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "10.973 ns" { mclk div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.973 ns" { mclk mclk~combout div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[1] } { 0.000ns 0.000ns 5.202ns 2.427ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "10.973 ns" { mclk div_256:inst1|clk ps2_keyboard_interface:inst3|q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.973 ns" { mclk mclk~combout div_256:inst1|clk ps2_keyboard_interface:inst3|q[2] } { 0.000ns 0.000ns 5.202ns 2.427ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 228 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 191 -1 0 } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "14.919 ns" { ps2_keyboard_interface:inst3|q[2] ps2_keyboard_interface:inst3|reduce_nor~4904 ps2_keyboard_interface:inst3|reduce_nor~4932 ps2_keyboard_interface:inst3|reduce_or~1281 ps2_keyboard_interface:inst3|reduce_or~1282 ps2_keyboard_interface:inst3|reduce_nor~4958 ps2_keyboard_interface:inst3|reduce_nor~104 ps2_keyboard_interface:inst3|reduce_or~1287 ps2_keyboard_interface:inst3|rx_ascii[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "14.919 ns" { ps2_keyboard_interface:inst3|q[2] ps2_keyboard_interface:inst3|reduce_nor~4904 ps2_keyboard_interface:inst3|reduce_nor~4932 ps2_keyboard_interface:inst3|reduce_or~1281 ps2_keyboard_interface:inst3|reduce_or~1282 ps2_keyboard_interface:inst3|reduce_nor~4958 ps2_keyboard_interface:inst3|reduce_nor~104 ps2_keyboard_interface:inst3|reduce_or~1287 ps2_keyboard_interface:inst3|rx_ascii[1] } { 0.000ns 0.972ns 2.678ns 0.784ns 2.047ns 0.737ns 1.999ns 0.305ns 1.180ns } { 0.000ns 0.740ns 0.200ns 0.511ns 0.511ns 0.740ns 0.511ns 0.200ns 0.804ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "10.973 ns" { mclk div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.973 ns" { mclk mclk~combout div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[1] } { 0.000ns 0.000ns 5.202ns 2.427ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/PS2/PROJ/" "" "10.973 ns" { mclk div_256:inst1|clk ps2_keyboard_interface:inst3|q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.973 ns" { mclk mclk~combout div_256:inst1|clk ps2_keyboard_interface:inst3|q[2] } { 0.000ns 0.000ns 5.202ns 2.427ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0}