📄 i2c.fit.rpt
字号:
; Interconnect Resource Type ; Usage ;
+----------------------------+----------------------+
; C4s ; 171 / 2,870 ( 5 % ) ;
; Direct links ; 87 / 3,938 ( 2 % ) ;
; Global clocks ; 2 / 4 ( 50 % ) ;
; LAB clocks ; 16 / 72 ( 22 % ) ;
; LUT chains ; 38 / 1,143 ( 3 % ) ;
; Local interconnects ; 420 / 3,938 ( 10 % ) ;
; R4s ; 169 / 2,832 ( 5 % ) ;
+----------------------------+----------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 8.67) ; Number of LABs (Total = 30) ;
+--------------------------------------------+------------------------------+
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 3 ;
; 8 ; 1 ;
; 9 ; 8 ;
; 10 ; 15 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.67) ; Number of LABs (Total = 30) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 22 ;
; 1 Clock ; 22 ;
; 1 Clock enable ; 6 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 9.10) ; Number of LABs (Total = 30) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 2 ;
; 9 ; 6 ;
; 10 ; 14 ;
; 11 ; 2 ;
; 12 ; 1 ;
; 13 ; 1 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 6.03) ; Number of LABs (Total = 30) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 3 ;
; 3 ; 1 ;
; 4 ; 4 ;
; 5 ; 3 ;
; 6 ; 4 ;
; 7 ; 4 ;
; 8 ; 4 ;
; 9 ; 4 ;
; 10 ; 2 ;
+-------------------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 14.03) ; Number of LABs (Total = 30) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 3 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 2 ;
; 11 ; 4 ;
; 12 ; 1 ;
; 13 ; 0 ;
; 14 ; 1 ;
; 15 ; 1 ;
; 16 ; 2 ;
; 17 ; 2 ;
; 18 ; 0 ;
; 19 ; 3 ;
; 20 ; 3 ;
; 21 ; 2 ;
; 22 ; 2 ;
+----------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Sat Feb 18 13:20:42 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off i2c -c i2c
Info: Selected device EPM1270T144C5 for design "i2c"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EPM570T144C5 is compatible
Info: Device EPM570T144I5 is compatible
Info: Device EPM1270T144I5 is compatible
Info: Device EPM1270T144C5ES is compatible
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock
Info: Pin "clk" drives global clock, but is not placed in a dedicated clock pin position
Info: Automatically promoted signal "rst" to use Global clock
Info: Pin "rst" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Warning: Ignored locations or region assignments to the following nodes
Warning: Node "data_in[4]" is assigned to location or region, but does not exist in design
Warning: Node "data_in[5]" is assigned to location or region, but does not exist in design
Warning: Node "data_in[6]" is assigned to location or region, but does not exist in design
Warning: Node "data_in[7]" is assigned to location or region, but does not exist in design
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 9.444 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X12_Y6; Fanout = 9; REG Node = 'inner_state.seventh'
Info: 2: + IC(2.103 ns) + CELL(0.511 ns) = 2.614 ns; Loc. = LAB_X13_Y5; Fanout = 4; COMB Node = 'Select~18637'
Info: 3: + IC(2.812 ns) + CELL(0.200 ns) = 5.626 ns; Loc. = LAB_X10_Y7; Fanout = 1; COMB Node = 'Select~18653'
Info: 4: + IC(0.269 ns) + CELL(0.914 ns) = 6.809 ns; Loc. = LAB_X10_Y7; Fanout = 1; COMB Node = 'Select~18657'
Info: 5: + IC(0.443 ns) + CELL(0.740 ns) = 7.992 ns; Loc. = LAB_X10_Y7; Fanout = 1; COMB Node = 'Select~18660'
Info: 6: + IC(0.269 ns) + CELL(1.183 ns) = 9.444 ns; Loc. = LAB_X10_Y7; Fanout = 12; REG Node = 'link'
Info: Total cell delay = 3.548 ns ( 37.57 % )
Info: Total interconnect delay = 5.896 ns ( 62.43 % )
Info: Fitter placement operations ending: elapsed time is 00:00:04
Info: Fitter routing operations beginning
Info: Average interconnect usage is 5% of the available device resources. Peak interconnect usage is 8%.
Info: Fitter routing operations ending: elapsed time is 00:00:02
Info: The following groups of pins have the same output enable
Info: The following pins have the same output enable: link
Info: Type bidirectional pin sda uses the LVTTL I/O standard
Info: Quartus II Fitter was successful. 0 errors, 5 warnings
Info: Processing ended: Sat Feb 18 13:20:54 2006
Info: Elapsed time: 00:00:12
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -