i2c.tan.rpt

基于EPM1270的EProm at24c02 驱动

; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; fmax Requirement                                      ; 45.0 MHz           ;      ;    ;             ;
; Ignore Clock Settings                                 ; On                 ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; 45.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                     ;
+-----------------------------------------+-----------------------------------------------------+----------------------+---------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                 ; To                  ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------+---------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; 11.037 ns                               ; 89.41 MHz ( period = 11.185 ns )                    ; inner_state.start    ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 10.476 ns               ;
; 11.065 ns                               ; 89.63 MHz ( period = 11.157 ns )                    ; inner_state.stop     ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 10.448 ns               ;
; 11.354 ns                               ; 92.01 MHz ( period = 10.868 ns )                    ; inner_state.sixth    ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 10.159 ns               ;
; 11.500 ns                               ; 93.27 MHz ( period = 10.722 ns )                    ; inner_state.first    ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 10.013 ns               ;
; 11.529 ns                               ; 93.52 MHz ( period = 10.693 ns )                    ; sda_buf              ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.984 ns                ;
; 11.608 ns                               ; 94.22 MHz ( period = 10.614 ns )                    ; inner_state.eighth   ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.905 ns                ;
; 11.658 ns                               ; 94.66 MHz ( period = 10.564 ns )                    ; inner_state.fifth    ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.855 ns                ;
; 11.769 ns                               ; 95.67 MHz ( period = 10.453 ns )                    ; inner_state.ack      ; main_state.00       ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.744 ns                ;
; 11.973 ns                               ; 97.57 MHz ( period = 10.249 ns )                    ; inner_state.fourth   ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.540 ns                ;
; 12.033 ns                               ; 98.15 MHz ( period = 10.189 ns )                    ; inner_state.third    ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.480 ns                ;
; 12.065 ns                               ; 98.45 MHz ( period = 10.157 ns )                    ; i2c_state.sendaddr   ; inner_state.ack     ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.448 ns                ;
; 12.077 ns                               ; 98.57 MHz ( period = 10.145 ns )                    ; inner_state.stop     ; inner_state.ack     ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.436 ns                ;
; 12.210 ns                               ; 99.88 MHz ( period = 10.012 ns )                    ; inner_state.sixth    ; link                ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.303 ns                ;
; 12.261 ns                               ; 100.39 MHz ( period = 9.961 ns )                    ; phase3               ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.252 ns                ;
; 12.264 ns                               ; 100.42 MHz ( period = 9.958 ns )                    ; clk_div[4]           ; phase3              ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.249 ns                ;
; 12.431 ns                               ; 102.13 MHz ( period = 9.791 ns )                    ; inner_state.start    ; inner_state.ack     ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.082 ns                ;
; 12.483 ns                               ; 102.68 MHz ( period = 9.739 ns )                    ; link                 ; link                ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.030 ns                ;
; 12.521 ns                               ; 103.08 MHz ( period = 9.701 ns )                    ; inner_state.seventh  ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.992 ns                ;
; 12.533 ns                               ; 103.21 MHz ( period = 9.689 ns )                    ; phase1               ; inner_state.ack     ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.980 ns                ;
; 12.538 ns                               ; 103.26 MHz ( period = 9.684 ns )                    ; inner_state.fourth   ; link                ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.975 ns                ;
; 12.543 ns                               ; 103.32 MHz ( period = 9.679 ns )                    ; phase1               ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.970 ns                ;
; 12.545 ns                               ; 103.34 MHz ( period = 9.677 ns )                    ; inner_state.ack      ; inner_state.ack     ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.968 ns                ;
; 12.688 ns                               ; 104.89 MHz ( period = 9.534 ns )                    ; inner_state.seventh  ; link                ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.825 ns                ;
; 12.708 ns                               ; 105.11 MHz ( period = 9.514 ns )                    ; i2c_state.write_data ; inner_state.ack     ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.805 ns                ;
; 12.749 ns                               ; 105.56 MHz ( period = 9.473 ns )                    ; inner_state.ack      ; main_state.01       ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.764 ns                ;
; 12.760 ns                               ; 105.69 MHz ( period = 9.462 ns )                    ; inner_state.ack      ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.753 ns                ;
; 12.775 ns                               ; 105.85 MHz ( period = 9.447 ns )                    ; inner_state.eighth   ; inner_state.ack     ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.738 ns                ;
; 12.857 ns                               ; 106.78 MHz ( period = 9.365 ns )                    ; inner_state.ack      ; link                ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.656 ns                ;
; 12.940 ns                               ; 107.74 MHz ( period = 9.282 ns )                    ; i2c_state.read_data  ; inner_state.fourth  ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.573 ns                ;
; 13.005 ns                               ; 108.50 MHz ( period = 9.217 ns )                    ; inner_state.second   ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.508 ns                ;
; 13.060 ns                               ; 109.15 MHz ( period = 9.162 ns )                    ; i2c_state.ini        ; inner_state.ack     ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.453 ns                ;
; 13.062 ns                               ; 109.17 MHz ( period = 9.160 ns )                    ; inner_state.stop     ; link                ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.451 ns                ;
; 13.092 ns                               ; 109.53 MHz ( period = 9.130 ns )                    ; main_state.01        ; main_state.00       ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.421 ns                ;
; 13.124 ns                               ; 109.91 MHz ( period = 9.098 ns )                    ; inner_state.ack      ; main_state.10       ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.389 ns                ;
; 13.129 ns                               ; 109.97 MHz ( period = 9.093 ns )                    ; i2c_state.read_ini   ; main_state.00       ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.384 ns                ;
; 13.163 ns                               ; 110.39 MHz ( period = 9.059 ns )                    ; inner_state.first    ; link                ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.350 ns                ;