mult_9r01.tdf

自己编写的8254计数器／计时器

--lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEDICATED_MULTIPLIER_CIRCUITRY="AUTO" DEVICE_FAMILY="Stratix II" DSP_BLOCK_BALANCING="Auto" INPUT_A_IS_CONSTANT="YES" INPUT_B_IS_CONSTANT="NO" LPM_REPRESENTATION="SIGNED" LPM_WIDTHA=8 LPM_WIDTHB=32 LPM_WIDTHP=40 LPM_WIDTHS=1 MAXIMIZE_SPEED=5 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 7.2 cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_mult 2007:07:20:16:47:26:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_padd 2007:07:12:14:48:24:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ  VERSION_END


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FUNCTION stratixii_mac_mult (aclr[3..0], clk[3..0], dataa[dataa_width-1..0], datab[datab_width-1..0], ena[3..0], mode, round, saturate, scanina[dataa_width-1..0], scaninb[datab_width-1..0], signa, signb, sourcea, sourceb, zeroacc)
WITH ( bypass_multiplier, dataa_clear, dataa_clock, dataa_width, datab_clear, datab_clock, datab_width, dynamic_mode, mode_clear, mode_clock, output_clear, output_clock, round_clear, round_clock, saturate_clear, saturate_clock, signa_clear, signa_clock, signa_internally_grounded, signb_clear, signb_clock, signb_internally_grounded, zeroacc_clear, zeroacc_clock)
RETURNS ( dataout[dataa_width+datab_width-1..0], scanouta[dataa_width-1..0], scanoutb[datab_width-1..0]);
FUNCTION stratixii_mac_out (aclr[3..0], addnsub0, addnsub1, clk[3..0], dataa[dataa_width-1..0], datab[datab_width-1..0], datac[datac_width-1..0], datad[datad_width-1..0], ena[3..0], mode0, mode1, multabsaturate, multcdsaturate, round0, round1, saturate, saturate1, signa, signb, zeroacc, zeroacc1)
WITH ( addnsub0_clear, addnsub0_clock, addnsub0_pipeline_clear, addnsub0_pipeline_clock, addnsub1_clear, addnsub1_clock, addnsub1_pipeline_clear, addnsub1_pipeline_clock, dataa_forced_to_zero, dataa_width = 1, datab_width = 1, datac_forced_to_zero, datac_width = 1, datad_width = 1, dataout_width = 144, mode0_clear, mode0_clock, mode0_pipeline_clear, mode0_pipeline_clock, mode1_clear, mode1_clock, mode1_pipeline_clear, mode1_pipeline_clock, multabsaturate_clear, multabsaturate_clock, multabsaturate_pipeline_clear, multabsaturate_pipeline_clock, multcdsaturate_clear, multcdsaturate_clock, multcdsaturate_pipeline_clear, multcdsaturate_pipeline_clock, operation_mode, output1_clear, output1_clock, output2_clear, output2_clock, output3_clear, output3_clock, output4_clear, output4_clock, output5_clear, output5_clock, output6_clear, output6_clock, output7_clear, output7_clock, output_clear, output_clock, round0_clear, round0_clock, round0_pipeline_clear, round0_pipeline_clock, round1_clear, round1_clock, round1_pipeline_clear, round1_pipeline_clock, saturate1_clear, saturate1_clock, saturate1_pipeline_clear, saturate1_pipeline_clock, saturate_clear, saturate_clock, saturate_pipeline_clear, saturate_pipeline_clock, signa_clear, signa_clock, signa_pipeline_clear, signa_pipeline_clock, signb_clear, signb_clock, signb_pipeline_clear, signb_pipeline_clock, zeroacc1_clear, zeroacc1_clock, zeroacc1_pipeline_clear, zeroacc1_pipeline_clock, zeroacc_clear, zeroacc_clock, zeroacc_pipeline_clear, zeroacc_pipeline_clock)
RETURNS ( accoverflow, dataout[dataout_width-1..0]);

--synthesis_resources = dsp_9bit 8 
SUBDESIGN mult_9r01
( 
	dataa[7..0]	:	input;
	datab[31..0]	:	input;
	result[39..0]	:	output;
) 
VARIABLE 
	mac_mult1 : stratixii_mac_mult
		WITH (
			dataa_width = 18,
			datab_width = 18,
			signa_internally_grounded = "true",
			signb_internally_grounded = "true"
		);
	mac_mult2 : stratixii_mac_mult
		WITH (
			dataa_width = 18,
			datab_width = 18
		);
	mac_mult3 : stratixii_mac_mult
		WITH (
			dataa_width = 18,
			datab_width = 18,
			signb_internally_grounded = "true"
		);
	mac_mult4 : stratixii_mac_mult
		WITH (
			dataa_width = 18,
			datab_width = 18,
			signa_internally_grounded = "true"
		);
	mac_out5 : stratixii_mac_out
		WITH (
			dataa_width = 36,
			datab_width = 36,
			datac_width = 36,
			datad_width = 36,
			dataout_width = 144,
			operation_mode = "36_bit_multiply"
		);
	aclr	: NODE;
	clken	: NODE;
	clock	: NODE;

BEGIN 
	mac_mult1.aclr[] = aclr;
	mac_mult1.clk[] = clock;
	mac_mult1.dataa[] = B"000000000000000000";
	mac_mult1.datab[] = ( datab[13..0], B"0000");
	mac_mult1.ena[] = clken;
	mac_mult1.signa = B"1";
	mac_mult1.signb = B"1";
	mac_mult2.aclr[] = aclr;
	mac_mult2.clk[] = clock;
	mac_mult2.dataa[] = ( dataa[], B"0000000000");
	mac_mult2.datab[17..0] = datab[31..14];
	mac_mult2.ena[] = clken;
	mac_mult2.signa = B"1";
	mac_mult2.signb = B"1";
	mac_mult3.aclr[] = aclr;
	mac_mult3.clk[] = clock;
	mac_mult3.dataa[] = ( dataa[], B"0000000000");
	mac_mult3.datab[] = ( datab[13..0], B"0000");
	mac_mult3.ena[] = clken;
	mac_mult3.signa = B"1";
	mac_mult3.signb = B"1";
	mac_mult4.aclr[] = aclr;
	mac_mult4.clk[] = clock;
	mac_mult4.dataa[] = B"000000000000000000";
	mac_mult4.datab[17..0] = datab[31..14];
	mac_mult4.ena[] = clken;
	mac_mult4.signa = B"1";
	mac_mult4.signb = B"1";
	mac_out5.aclr[] = aclr;
	mac_out5.clk[] = clock;
	mac_out5.dataa[] = mac_mult1.dataout[];
	mac_out5.datab[] = mac_mult2.dataout[];
	mac_out5.datac[] = mac_mult3.dataout[];
	mac_out5.datad[] = mac_mult4.dataout[];
	mac_out5.ena[] = clken;
	mac_out5.signa = B"1";
	mac_out5.signb = B"1";
	aclr = GND;
	clken = VCC;
	clock = GND;
	result[39..0] = mac_out5.dataout[71..32];
END;
--VALID FILE