a8254.tan.qmsg

自己编写的8254计数器／计时器

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK out_sgnl\[2\] cnt_main_part:a8254_2\|out_sgnl\[2\] 6.425 ns register " "Info: tco from clock \"CLK\" to destination pin \"out_sgnl\[2\]\" through register \"cnt_main_part:a8254_2\|out_sgnl\[2\]\" is 6.425 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.479 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.479 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "a8254top.vhd" "" { Text "E:/a8254/a8254top.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 227 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 227; COMB Node = 'CLK~clkctrl'" {  } { { "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "a8254top.vhd" "" { Text "E:/a8254/a8254top.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.664 ns) + CELL(0.618 ns) 2.479 ns cnt_main_part:a8254_2\|out_sgnl\[2\] 3 REG LCFF_X25_Y16_N17 3 " "Info: 3: + IC(0.664 ns) + CELL(0.618 ns) = 2.479 ns; Loc. = LCFF_X25_Y16_N17; Fanout = 3; REG Node = 'cnt_main_part:a8254_2\|out_sgnl\[2\]'" {  } { { "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.282 ns" { CLK~clkctrl cnt_main_part:a8254_2|out_sgnl[2] } "NODE_NAME" } } { "cnt_main_part.vhd" "" { Text "E:/a8254/cnt_main_part.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.38 % ) " "Info: Total cell delay = 1.472 ns ( 59.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.007 ns ( 40.62 % ) " "Info: Total interconnect delay = 1.007 ns ( 40.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.479 ns" { CLK CLK~clkctrl cnt_main_part:a8254_2|out_sgnl[2] } "NODE_NAME" } } { "d:/program files/quaruts ii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quaruts ii7.2/quartus/bin/Technology_Viewer.qrui" "2.479 ns" { CLK {} CLK~combout {} CLK~clkctrl {} cnt_main_part:a8254_2|out_sgnl[2] {} } { 0.000ns 0.000ns 0.343ns 0.664ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "cnt_main_part.vhd" "" { Text "E:/a8254/cnt_main_part.vhd" 66 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.852 ns + Longest register pin " "Info: + Longest register to pin delay is 3.852 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt_main_part:a8254_2\|out_sgnl\[2\] 1 REG LCFF_X25_Y16_N17 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y16_N17; Fanout = 3; REG Node = 'cnt_main_part:a8254_2\|out_sgnl\[2\]'" {  } { { "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_main_part:a8254_2|out_sgnl[2] } "NODE_NAME" } } { "cnt_main_part.vhd" "" { Text "E:/a8254/cnt_main_part.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.708 ns) + CELL(2.144 ns) 3.852 ns out_sgnl\[2\] 2 PIN PIN_L20 0 " "Info: 2: + IC(1.708 ns) + CELL(2.144 ns) = 3.852 ns; Loc. = PIN_L20; Fanout = 0; PIN Node = 'out_sgnl\[2\]'" {  } { { "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.852 ns" { cnt_main_part:a8254_2|out_sgnl[2] out_sgnl[2] } "NODE_NAME" } } { "a8254top.vhd" "" { Text "E:/a8254/a8254top.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.144 ns ( 55.66 % ) " "Info: Total cell delay = 2.144 ns ( 55.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.708 ns ( 44.34 % ) " "Info: Total interconnect delay = 1.708 ns ( 44.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.852 ns" { cnt_main_part:a8254_2|out_sgnl[2] out_sgnl[2] } "NODE_NAME" } } { "d:/program files/quaruts ii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quaruts ii7.2/quartus/bin/Technology_Viewer.qrui" "3.852 ns" { cnt_main_part:a8254_2|out_sgnl[2] {} out_sgnl[2] {} } { 0.000ns 1.708ns } { 0.000ns 2.144ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.479 ns" { CLK CLK~clkctrl cnt_main_part:a8254_2|out_sgnl[2] } "NODE_NAME" } } { "d:/program files/quaruts ii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quaruts ii7.2/quartus/bin/Technology_Viewer.qrui" "2.479 ns" { CLK {} CLK~combout {} CLK~clkctrl {} cnt_main_part:a8254_2|out_sgnl[2] {} } { 0.000ns 0.000ns 0.343ns 0.664ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.852 ns" { cnt_main_part:a8254_2|out_sgnl[2] out_sgnl[2] } "NODE_NAME" } } { "d:/program files/quaruts ii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quaruts ii7.2/quartus/bin/Technology_Viewer.qrui" "3.852 ns" { cnt_main_part:a8254_2|out_sgnl[2] {} out_sgnl[2] {} } { 0.000ns 1.708ns } { 0.000ns 2.144ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "cnt_main_part:a8254_2\|countmsb1\[6\] data\[6\] CLK 0.012 ns register " "Info: th for register \"cnt_main_part:a8254_2\|countmsb1\[6\]\" (data pin = \"data\[6\]\", clock pin = \"CLK\") is 0.012 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.485 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.485 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "a8254top.vhd" "" { Text "E:/a8254/a8254top.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 227 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 227; COMB Node = 'CLK~clkctrl'" {  } { { "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "a8254top.vhd" "" { Text "E:/a8254/a8254top.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.670 ns) + CELL(0.618 ns) 2.485 ns cnt_main_part:a8254_2\|countmsb1\[6\] 3 REG LCFF_X27_Y15_N9 1 " "Info: 3: + IC(0.670 ns) + CELL(0.618 ns) = 2.485 ns; Loc. = LCFF_X27_Y15_N9; Fanout = 1; REG Node = 'cnt_main_part:a8254_2\|countmsb1\[6\]'" {  } { { "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.288 ns" { CLK~clkctrl cnt_main_part:a8254_2|countmsb1[6] } "NODE_NAME" } } { "cnt_main_part.vhd" "" { Text "E:/a8254/cnt_main_part.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.24 % ) " "Info: Total cell delay = 1.472 ns ( 59.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.013 ns ( 40.76 % ) " "Info: Total interconnect delay = 1.013 ns ( 40.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.485 ns" { CLK CLK~clkctrl cnt_main_part:a8254_2|countmsb1[6] } "NODE_NAME" } } { "d:/program files/quaruts ii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quaruts ii7.2/quartus/bin/Technology_Viewer.qrui" "2.485 ns" { CLK {} CLK~combout {} CLK~clkctrl {} cnt_main_part:a8254_2|countmsb1[6] {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" {  } { { "cnt_main_part.vhd" "" { Text "E:/a8254/cnt_main_part.vhd" 66 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.622 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.622 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns data\[6\] 1 PIN PIN_M21 7 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 7; PIN Node = 'data\[6\]'" {  } { { "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[6] } "NODE_NAME" } } { "a8254top.vhd" "" { Text "E:/a8254/a8254top.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.449 ns) + CELL(0.309 ns) 2.622 ns cnt_main_part:a8254_2\|countmsb1\[6\] 2 REG LCFF_X27_Y15_N9 1 " "Info: 2: + IC(1.449 ns) + CELL(0.309 ns) = 2.622 ns; Loc. = LCFF_X27_Y15_N9; Fanout = 1; REG Node = 'cnt_main_part:a8254_2\|countmsb1\[6\]'" {  } { { "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quaruts ii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.758 ns" { data[6] cnt_main_part:a8254_2|countmsb1[6] } "NODE_NAME" } } { "cnt_main_part.vhd" "" { Text "E:/a8254/cnt_main_part.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!