a8254top.fnsim.qmsg

自己编写的8254计数器／计时器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 30 12:54:31 2008 " "Info: Processing started: Sat Aug 30 12:54:31 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off a8254top -c a8254top --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off a8254top -c a8254top --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "my_lib/mode_set.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file my_lib/mode_set.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mode_set " "Info: Found design unit 1: mode_set" {  } { { "my_lib/mode_set.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/my_lib/mode_set.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 mode_set-body " "Info: Found design unit 2: mode_set-body" {  } { { "my_lib/mode_set.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/my_lib/mode_set.vhd" 50 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "a8254top.vhd 2 1 " "Warning: Using design file a8254top.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 a8254top-main_part " "Info: Found design unit 1: a8254top-main_part" {  } { { "a8254top.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/a8254top.vhd" 28 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 a8254top " "Info: Found entity 1: a8254top" {  } { { "a8254top.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/a8254top.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "a8254top " "Info: Elaborating entity \"a8254top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "mode_reg.vhd 2 1 " "Warning: Using design file mode_reg.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mode_reg-main " "Info: Found design unit 1: mode_reg-main" {  } { { "mode_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/mode_reg.vhd" 27 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 mode_reg " "Info: Found entity 1: mode_reg" {  } { { "mode_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/mode_reg.vhd" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mode_reg mode_reg:a8254_1 " "Info: Elaborating entity \"mode_reg\" for hierarchy \"mode_reg:a8254_1\"" {  } { { "a8254top.vhd" "a8254_1" { Text "D:/gaochao/LNG/digitalogic/a8254top/a8254top.vhd" 137 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "cnt_choice mode_reg.vhd(37) " "Warning (10631): VHDL Process Statement warning at mode_reg.vhd(37): inferring latch(es) for signal or variable \"cnt_choice\", which holds its previous value in one or more paths through the process" {  } { { "mode_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/mode_reg.vhd" 37 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "rwmode mode_reg.vhd(37) " "Warning (10631): VHDL Process Statement warning at mode_reg.vhd(37): inferring latch(es) for signal or variable \"rwmode\", which holds its previous value in one or more paths through the process" {  } { { "mode_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/mode_reg.vhd" 37 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "mode_choice mode_reg.vhd(37) " "Warning (10631): VHDL Process Statement warning at mode_reg.vhd(37): inferring latch(es) for signal or variable \"mode_choice\", which holds its previous value in one or more paths through the process" {  } { { "mode_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/mode_reg.vhd" 37 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "binnbcd mode_reg.vhd(37) " "Warning (10631): VHDL Process Statement warning at mode_reg.vhd(37): inferring latch(es) for signal or variable \"binnbcd\", which holds its previous value in one or more paths through the process" {  } { { "mode_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/mode_reg.vhd" 37 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "binnbcd mode_reg.vhd(37) " "Info (10041): Inferred latch for \"binnbcd\" at mode_reg.vhd(37)" {  } { { "mode_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/mode_reg.vhd" 37 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "mode_choice\[0\] mode_reg.vhd(37) " "Info (10041): Inferred latch for \"mode_choice\[0\]\" at mode_reg.vhd(37)" {  } { { "mode_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/mode_reg.vhd" 37 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "mode_choice\[1\] mode_reg.vhd(37) " "Info (10041): Inferred latch for \"mode_choice\[1\]\" at mode_reg.vhd(37)" {  } { { "mode_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/mode_reg.vhd" 37 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "mode_choice\[2\] mode_reg.vhd(37) " "Info (10041): Inferred latch for \"mode_choice\[2\]\" at mode_reg.vhd(37)" {  } { { "mode_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/mode_reg.vhd" 37 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rwmode\[0\] mode_reg.vhd(37) " "Info (10041): Inferred latch for \"rwmode\[0\]\" at mode_reg.vhd(37)" {  } { { "mode_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/mode_reg.vhd" 37 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rwmode\[1\] mode_reg.vhd(37) " "Info (10041): Inferred latch for \"rwmode\[1\]\" at mode_reg.vhd(37)" {  } { { "mode_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/mode_reg.vhd" 37 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "cnt_choice\[0\] mode_reg.vhd(37) " "Info (10041): Inferred latch for \"cnt_choice\[0\]\" at mode_reg.vhd(37)" {  } { { "mode_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/mode_reg.vhd" 37 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "cnt_choice\[1\] mode_reg.vhd(37) " "Info (10041): Inferred latch for \"cnt_choice\[1\]\" at mode_reg.vhd(37)" {  } { { "mode_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/mode_reg.vhd" 37 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "cnt_reg.vhd 2 1 " "Warning: Using design file cnt_reg.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cnt_reg-main " "Info: Found design unit 1: cnt_reg-main" {  } { { "cnt_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/cnt_reg.vhd" 39 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 cnt_reg " "Info: Found entity 1: cnt_reg" {  } { { "cnt_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/cnt_reg.vhd" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cnt_reg cnt_reg:a8254_2 " "Info: Elaborating entity \"cnt_reg\" for hierarchy \"cnt_reg:a8254_2\"" {  } { { "a8254top.vhd" "a8254_2" { Text "D:/gaochao/LNG/digitalogic/a8254top/a8254top.vhd" 151 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data cnt_reg.vhd(57) " "Warning (10492): VHDL Process Statement warning at cnt_reg.vhd(57): signal \"data\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cnt_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/cnt_reg.vhd" 57 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data cnt_reg.vhd(59) " "Warning (10492): VHDL Process Statement warning at cnt_reg.vhd(59): signal \"data\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cnt_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/cnt_reg.vhd" 59 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data cnt_reg.vhd(70) " "Warning (10492): VHDL Process Statement warning at cnt_reg.vhd(70): signal \"data\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cnt_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/cnt_reg.vhd" 70 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data cnt_reg.vhd(72) " "Warning (10492): VHDL Process Statement warning at cnt_reg.vhd(72): signal \"data\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cnt_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/cnt_reg.vhd" 72 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data cnt_reg.vhd(83) " "Warning (10492): VHDL Process Statement warning at cnt_reg.vhd(83): signal \"data\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cnt_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/cnt_reg.vhd" 83 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data cnt_reg.vhd(85) " "Warning (10492): VHDL Process Statement warning at cnt_reg.vhd(85): signal \"data\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cnt_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/cnt_reg.vhd" 85 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "countlsb0 cnt_reg.vhd(53) " "Warning (10631): VHDL Process Statement warning at cnt_reg.vhd(53): inferring latch(es) for signal or variable \"countlsb0\", which holds its previous value in one or more paths through the process" {  } { { "cnt_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/cnt_reg.vhd" 53 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "countmsb0 cnt_reg.vhd(53) " "Warning (10631): VHDL Process Statement warning at cnt_reg.vhd(53): inferring latch(es) for signal or variable \"countmsb0\", which holds its previous value in one or more paths through the process" {  } { { "cnt_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/cnt_reg.vhd" 53 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "countlsb1 cnt_reg.vhd(53) " "Warning (10631): VHDL Process Statement warning at cnt_reg.vhd(53): inferring latch(es) for signal or variable \"countlsb1\", which holds its previous value in one or more paths through the process" {  } { { "cnt_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/cnt_reg.vhd" 53 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "countmsb1 cnt_reg.vhd(53) " "Warning (10631): VHDL Process Statement warning at cnt_reg.vhd(53): inferring latch(es) for signal or variable \"countmsb1\", which holds its previous value in one or more paths through the process" {  } { { "cnt_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/cnt_reg.vhd" 53 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "countlsb2 cnt_reg.vhd(53) " "Warning (10631): VHDL Process Statement warning at cnt_reg.vhd(53): inferring latch(es) for signal or variable \"countlsb2\", which holds its previous value in one or more paths through the process" {  } { { "cnt_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/cnt_reg.vhd" 53 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "countmsb2 cnt_reg.vhd(53) " "Warning (10631): VHDL Process Statement warning at cnt_reg.vhd(53): inferring latch(es) for signal or variable \"countmsb2\", which holds its previous value in one or more paths through the process" {  } { { "cnt_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/cnt_reg.vhd" 53 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_SYNTHESIS_IGNORED_CHOICE_WITH_META_VALUE" "\"X10\" cnt_reg.vhd(119) " "Warning (10325): VHDL Choice warning at cnt_reg.vhd(119): ignored choice containing meta-value \"\"X10\"\"" {  } { { "cnt_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/cnt_reg.vhd" 119 0 0 } }  } 0 10325 "VHDL Choice warning at %2!s!: ignored choice containing meta-value \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_SYNTHESIS_IGNORED_CHOICE_WITH_META_VALUE" "\"X11\" cnt_reg.vhd(122) " "Warning (10325): VHDL Choice warning at cnt_reg.vhd(122): ignored choice containing meta-value \"\"X11\"\"" {  } { { "cnt_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/cnt_reg.vhd" 122 0 0 } }  } 0 10325 "VHDL Choice warning at %2!s!: ignored choice containing meta-value \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CE_0 cnt_reg.vhd(112) " "Warning (10492): VHDL Process Statement warning at cnt_reg.vhd(112): signal \"CE_0\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cnt_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/cnt_reg.vhd" 112 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CE_1 cnt_reg.vhd(113) " "Warning (10492): VHDL Process Statement warning at cnt_reg.vhd(113): signal \"CE_1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cnt_reg.vhd" "" { Text "D:/gaochao/LNG/digitalogic/a8254top/cnt_reg.vhd" 113 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}