a8254.fit.rpt

自己编写的8254计数器／计时器

Fitter report for a8254
Tue Sep 02 10:09:48 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Netlist Optimizations
  5. HardCopy II Device Resource Guide
  6. Pin-Out File
  7. Fitter Resource Usage Summary
  8. Input Pins
  9. Output Pins
 10. I/O Bank Usage
 11. All Package Pins
 12. Output Pin Default Load For Reported TCO
 13. Fitter Resource Utilization by Entity
 14. Delay Chain Summary
 15. Pad To Core Delay Chain Fanout
 16. Control Signals
 17. Global & Other Fast Signals
 18. Non-Global High Fan-Out Signals
 19. Fitter DSP Block Usage Summary
 20. DSP Block Details
 21. Interconnect Usage Summary
 22. LAB Logic Elements
 23. LAB-wide Signals
 24. LAB Signals Sourced
 25. LAB Signals Sourced Out
 26. LAB Distinct Inputs
 27. I/O Rules Summary
 28. I/O Rules Details
 29. I/O Rules Matrix
 30. Fitter Device Options
 31. Operating Settings and Conditions
 32. Advanced Data - General
 33. Advanced Data - Placement Preparation
 34. Advanced Data - Placement
 35. Advanced Data - Routing
 36. Fitter Messages
 37. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------+
; Fitter Summary                                                           ;
+-------------------------------+------------------------------------------+
; Fitter Status                 ; Successful - Tue Sep 02 10:09:48 2008    ;
; Quartus II Version            ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name                 ; a8254                                    ;
; Top-level Entity Name         ; a8254                                    ;
; Family                        ; Stratix II                               ;
; Device                        ; EP2S15F484C3                             ;
; Timing Models                 ; Final                                    ;
; Logic utilization             ; 5 %                                      ;
;     Combinational ALUTs       ; 524 / 12,480 ( 4 % )                     ;
;     Dedicated logic registers ; 227 / 12,480 ( 2 % )                     ;
; Total registers               ; 227                                      ;
; Total pins                    ; 20 / 343 ( 6 % )                         ;
; Total virtual pins            ; 0                                        ;
; Total block memory bits       ; 0 / 419,328 ( 0 % )                      ;
; DSP block 9-bit elements      ; 16 / 96 ( 17 % )                         ;
; Total PLLs                    ; 0 / 6 ( 0 % )                            ;
; Total DLLs                    ; 0 / 2 ( 0 % )                            ;
+-------------------------------+------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                         ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                                ; Setting                        ; Default Value                  ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                                ; AUTO                           ;                                ;
; Fit Attempts to Skip                                                  ; 0                              ; 0.0                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                   ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                         ; Off                            ; Off                            ;
; Router Timing Optimization Level                                      ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                           ; Off                            ; Off                            ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;