a8254.tan.rpt

来自「自己编写的8254计数器／计时器」· RPT 代码 · 共 291 行 · 第 1/5 页

; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                        ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------+----------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                 ; To                                     ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------+----------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 93.49 MHz ( period = 10.696 ns )                    ; cnt_main_part:a8254_2|bcd3[1]        ; cnt_main_part:a8254_2|ce0[31]          ; CLK        ; CLK      ; None                        ; None                      ; 10.510 ns               ;
; N/A                                     ; 95.30 MHz ( period = 10.493 ns )                    ; cnt_main_part:a8254_2|bcd3[2]        ; cnt_main_part:a8254_2|ce0[31]          ; CLK        ; CLK      ; None                        ; None                      ; 10.310 ns               ;
; N/A                                     ; 96.59 MHz ( period = 10.353 ns )                    ; cnt_main_part:a8254_2|bcd3[1]        ; cnt_main_part:a8254_2|ce0[16]          ; CLK        ; CLK      ; None                        ; None                      ; 10.162 ns               ;
; N/A                                     ; 97.48 MHz ( period = 10.259 ns )                    ; cnt_main_part:a8254_2|bcd3[0]        ; cnt_main_part:a8254_2|ce0[31]          ; CLK        ; CLK      ; None                        ; None                      ; 10.075 ns               ;
; N/A                                     ; 97.53 MHz ( period = 10.253 ns )                    ; cnt_main_part:a8254_2|bcd3[3]        ; cnt_main_part:a8254_2|ce0[31]          ; CLK        ; CLK      ; None                        ; None                      ; 10.069 ns               ;
; N/A                                     ; 98.52 MHz ( period = 10.150 ns )                    ; cnt_main_part:a8254_2|bcd3[2]        ; cnt_main_part:a8254_2|ce0[16]          ; CLK        ; CLK      ; None                        ; None                      ; 9.962 ns                ;
; N/A                                     ; 98.79 MHz ( period = 10.122 ns )                    ; cnt_main_part:a8254_2|bcd2[3]        ; cnt_main_part:a8254_2|ce0[31]          ; CLK        ; CLK      ; None                        ; None                      ; 9.943 ns                ;
; N/A                                     ; 100.24 MHz ( period = 9.976 ns )                    ; cnt_main_part:a8254_2|bcd2[1]        ; cnt_main_part:a8254_2|ce0[31]          ; CLK        ; CLK      ; None                        ; None                      ; 9.790 ns                ;
; N/A                                     ; 100.85 MHz ( period = 9.916 ns )                    ; cnt_main_part:a8254_2|bcd3[0]        ; cnt_main_part:a8254_2|ce0[16]          ; CLK        ; CLK      ; None                        ; None                      ; 9.727 ns                ;
; N/A                                     ; 100.91 MHz ( period = 9.910 ns )                    ; cnt_main_part:a8254_2|bcd3[3]        ; cnt_main_part:a8254_2|ce0[16]          ; CLK        ; CLK      ; None                        ; None                      ; 9.721 ns                ;
; N/A                                     ; 102.16 MHz ( period = 9.789 ns )                    ; cnt_main_part:a8254_2|ce0[1]         ; cnt_main_part:a8254_2|cee[1]           ; CLK        ; CLK      ; None                        ; None                      ; 9.588 ns                ;
; N/A                                     ; 102.16 MHz ( period = 9.789 ns )                    ; cnt_main_part:a8254_2|ce0[1]         ; cnt_main_part:a8254_2|cee[0]           ; CLK        ; CLK      ; None                        ; None                      ; 9.588 ns                ;
; N/A                                     ; 102.16 MHz ( period = 9.789 ns )                    ; cnt_main_part:a8254_2|ce0[1]         ; cnt_main_part:a8254_2|cee[1]~DUPLICATE ; CLK        ; CLK      ; None                        ; None                      ; 9.588 ns                ;
; N/A                                     ; 102.26 MHz ( period = 9.779 ns )                    ; cnt_main_part:a8254_2|bcd2[3]        ; cnt_main_part:a8254_2|ce0[16]          ; CLK        ; CLK      ; None                        ; None                      ; 9.595 ns                ;
; N/A                                     ; 102.42 MHz ( period = 9.764 ns )                    ; cnt_main_part:a8254_2|ce0[1]         ; cnt_main_part:a8254_2|cee[8]           ; CLK        ; CLK      ; None                        ; None                      ; 9.567 ns                ;
; N/A                                     ; 102.48 MHz ( period = 9.758 ns )                    ; cnt_main_part:a8254_2|ce0[2]         ; cnt_main_part:a8254_2|cee[1]           ; CLK        ; CLK      ; None                        ; None                      ; 9.557 ns                ;
; N/A                                     ; 102.48 MHz ( period = 9.758 ns )                    ; cnt_main_part:a8254_2|ce0[2]         ; cnt_main_part:a8254_2|cee[0]           ; CLK        ; CLK      ; None                        ; None                      ; 9.557 ns                ;
; N/A                                     ; 102.48 MHz ( period = 9.758 ns )                    ; cnt_main_part:a8254_2|ce0[2]         ; cnt_main_part:a8254_2|cee[1]~DUPLICATE ; CLK        ; CLK      ; None                        ; None                      ; 9.557 ns                ;
; N/A                                     ; 102.50 MHz ( period = 9.756 ns )                    ; cnt_main_part:a8254_2|ce0[1]         ; cnt_main_part:a8254_2|cee[31]          ; CLK        ; CLK      ; None                        ; None                      ; 9.555 ns                ;
; N/A                                     ; 102.51 MHz ( period = 9.755 ns )                    ; cnt_main_part:a8254_2|ce0[1]         ; cnt_main_part:a8254_2|cee[12]          ; CLK        ; CLK      ; None                        ; None                      ; 9.565 ns                ;
; N/A                                     ; 102.51 MHz ( period = 9.755 ns )                    ; cnt_main_part:a8254_2|ce0[1]         ; cnt_main_part:a8254_2|cee[13]          ; CLK        ; CLK      ; None                        ; None                      ; 9.565 ns                ;
; N/A                                     ; 102.55 MHz ( period = 9.751 ns )                    ; cnt_main_part:a8254_2|ce0[3]         ; cnt_main_part:a8254_2|cee[1]           ; CLK        ; CLK      ; None                        ; None                      ; 9.550 ns                ;
; N/A                                     ; 102.55 MHz ( period = 9.751 ns )                    ; cnt_main_part:a8254_2|ce0[3]         ; cnt_main_part:a8254_2|cee[0]           ; CLK        ; CLK      ; None                        ; None                      ; 9.550 ns                ;
; N/A                                     ; 102.55 MHz ( period = 9.751 ns )                    ; cnt_main_part:a8254_2|ce0[3]         ; cnt_main_part:a8254_2|cee[1]~DUPLICATE ; CLK        ; CLK      ; None                        ; None                      ; 9.550 ns                ;