a8254.tan.qmsg

来自「自己编写的8254计数器／计时器」· QMSG 代码 · 共 10 行 · 第 1/4 页

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK out_sgnl\[0\] cnt_main_part:a8254_3\|out_sgnl\[0\] 6.221 ns register " "Info: tco from clock \"CLK\" to destination pin \"out_sgnl\[0\]\" through register \"cnt_main_part:a8254_3\|out_sgnl\[0\]\" is 6.221 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.480 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.480 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "a8254.vhd" "" { Text "D:/gaochao/a8254/a8254/a8254.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 122 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 122; COMB Node = 'CLK~clkctrl'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "a8254.vhd" "" { Text "D:/gaochao/a8254/a8254/a8254.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.665 ns) + CELL(0.618 ns) 2.480 ns cnt_main_part:a8254_3\|out_sgnl\[0\] 3 REG LCFF_X30_Y10_N29 1 " "Info: 3: + IC(0.665 ns) + CELL(0.618 ns) = 2.480 ns; Loc. = LCFF_X30_Y10_N29; Fanout = 1; REG Node = 'cnt_main_part:a8254_3\|out_sgnl\[0\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.283 ns" { CLK~clkctrl cnt_main_part:a8254_3|out_sgnl[0] } "NODE_NAME" } } { "cnt_main_part.vhd" "" { Text "D:/gaochao/a8254/a8254/cnt_main_part.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.35 % ) " "Info: Total cell delay = 1.472 ns ( 59.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.008 ns ( 40.65 % ) " "Info: Total interconnect delay = 1.008 ns ( 40.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.480 ns" { CLK CLK~clkctrl cnt_main_part:a8254_3|out_sgnl[0] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "2.480 ns" { CLK {} CLK~combout {} CLK~clkctrl {} cnt_main_part:a8254_3|out_sgnl[0] {} } { 0.000ns 0.000ns 0.343ns 0.665ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "cnt_main_part.vhd" "" { Text "D:/gaochao/a8254/a8254/cnt_main_part.vhd" 52 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.647 ns + Longest register pin " "Info: + Longest register to pin delay is 3.647 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt_main_part:a8254_3\|out_sgnl\[0\] 1 REG LCFF_X30_Y10_N29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y10_N29; Fanout = 1; REG Node = 'cnt_main_part:a8254_3\|out_sgnl\[0\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_main_part:a8254_3|out_sgnl[0] } "NODE_NAME" } } { "cnt_main_part.vhd" "" { Text "D:/gaochao/a8254/a8254/cnt_main_part.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.695 ns) + CELL(1.952 ns) 3.647 ns out_sgnl\[0\] 2 PIN PIN_E10 0 " "Info: 2: + IC(1.695 ns) + CELL(1.952 ns) = 3.647 ns; Loc. = PIN_E10; Fanout = 0; PIN Node = 'out_sgnl\[0\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.647 ns" { cnt_main_part:a8254_3|out_sgnl[0] out_sgnl[0] } "NODE_NAME" } } { "a8254.vhd" "" { Text "D:/gaochao/a8254/a8254/a8254.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.952 ns ( 53.52 % ) " "Info: Total cell delay = 1.952 ns ( 53.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.695 ns ( 46.48 % ) " "Info: Total interconnect delay = 1.695 ns ( 46.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.647 ns" { cnt_main_part:a8254_3|out_sgnl[0] out_sgnl[0] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.647 ns" { cnt_main_part:a8254_3|out_sgnl[0] {} out_sgnl[0] {} } { 0.000ns 1.695ns } { 0.000ns 1.952ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.480 ns" { CLK CLK~clkctrl cnt_main_part:a8254_3|out_sgnl[0] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "2.480 ns" { CLK {} CLK~combout {} CLK~clkctrl {} cnt_main_part:a8254_3|out_sgnl[0] {} } { 0.000ns 0.000ns 0.343ns 0.665ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.647 ns" { cnt_main_part:a8254_3|out_sgnl[0] out_sgnl[0] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.647 ns" { cnt_main_part:a8254_3|out_sgnl[0] {} out_sgnl[0] {} } { 0.000ns 1.695ns } { 0.000ns 1.952ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "cnt_main_part:a8254_3\|gat gate\[0\] CLK -2.523 ns register " "Info: th for register \"cnt_main_part:a8254_3\|gat\" (data pin = \"gate\[0\]\", clock pin = \"CLK\") is -2.523 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.482 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.482 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "a8254.vhd" "" { Text "D:/gaochao/a8254/a8254/a8254.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 122 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 122; COMB Node = 'CLK~clkctrl'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "a8254.vhd" "" { Text "D:/gaochao/a8254/a8254/a8254.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.667 ns) + CELL(0.618 ns) 2.482 ns cnt_main_part:a8254_3\|gat 3 REG LCFF_X31_Y10_N9 1 " "Info: 3: + IC(0.667 ns) + CELL(0.618 ns) = 2.482 ns; Loc. = LCFF_X31_Y10_N9; Fanout = 1; REG Node = 'cnt_main_part:a8254_3\|gat'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.285 ns" { CLK~clkctrl cnt_main_part:a8254_3|gat } "NODE_NAME" } } { "cnt_main_part.vhd" "" { Text "D:/gaochao/a8254/a8254/cnt_main_part.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.31 % ) " "Info: Total cell delay = 1.472 ns ( 59.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.010 ns ( 40.69 % ) " "Info: Total interconnect delay = 1.010 ns ( 40.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.482 ns" { CLK CLK~clkctrl cnt_main_part:a8254_3|gat } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "2.482 ns" { CLK {} CLK~combout {} CLK~clkctrl {} cnt_main_part:a8254_3|gat {} } { 0.000ns 0.000ns 0.343ns 0.667ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" {  } { { "cnt_main_part.vhd" "" { Text "D:/gaochao/a8254/a8254/cnt_main_part.vhd" 43 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.154 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.154 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns gate\[0\] 1 PIN PIN_N1 28 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_N1; Fanout = 28; PIN Node = 'gate\[0\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { gate[0] } "NODE_NAME" } } { "a8254.vhd" "" { Text "D:/gaochao/a8254/a8254/a8254.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.981 ns) + CELL(0.309 ns) 5.154 ns cnt_main_part:a8254_3\|gat 2 REG LCFF_X31_Y10_N9 1 " "Info: 2: + IC(3.981 ns) + CELL(0.309 ns) = 5.154 ns; Loc. = LCFF_X31_Y10_N9; Fanout = 1; REG Node = 'cnt_main_part:a8254_3\|gat'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.290 ns" { gate[0] cnt_main_part:a8254_3|gat } "NODE_NAME" } } { "cnt_main_part.vhd" "" { Text "D:/gaochao/a8254/a8254/cnt_main_part.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.173 ns ( 22.76 % ) " "Info: Total cell delay = 1.173 ns ( 22.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.981 ns ( 77.24 % ) " "Info: Total interconnect delay = 3.981 ns ( 77.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.154 ns" { gate[0] cnt_main_part:a8254_3|gat } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "5.154 ns" { gate[0] {} gate[0]~combout {} cnt_main_part:a8254_3|gat {} } { 0.000ns 0.000ns 3.981ns } { 0.000ns 0.864ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.482 ns" { CLK CLK~clkctrl cnt_main_part:a8254_3|gat } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "2.482 ns" { CLK {} CLK~combout {} CLK~clkctrl {} cnt_main_part:a8254_3|gat {} } { 0.000ns 0.000ns 0.343ns 0.667ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.154 ns" { gate[0] cnt_main_part:a8254_3|gat } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "5.154 ns" { gate[0] {} gate[0]~combout {} cnt_main_part:a8254_3|gat {} } { 0.000ns 0.000ns 3.981ns } { 0.000ns 0.864ns 0.309ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "118 " "Info: Allocated 118 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 08 18:51:40 2008 " "Info: Processing ended: Mon Sep 08 18:51:40 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}