prev_cmp_a8254.tan.qmsg

来自「自己编写的8254计数器／计时器」· QMSG 代码 · 共 10 行 · 第 1/4 页

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK out_sgnl\[0\] cnt_main_part:a8254_3\|out_sgnl\[0\] 5.736 ns register " "Info: tco from clock \"CLK\" to destination pin \"out_sgnl\[0\]\" through register \"cnt_main_part:a8254_3\|out_sgnl\[0\]\" is 5.736 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.474 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.474 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "a8254.vhd" "" { Text "D:/gaochao/a8254/a8254/a8254.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 122 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 122; COMB Node = 'CLK~clkctrl'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "a8254.vhd" "" { Text "D:/gaochao/a8254/a8254/a8254.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.659 ns) + CELL(0.618 ns) 2.474 ns cnt_main_part:a8254_3\|out_sgnl\[0\] 3 REG LCFF_X27_Y7_N25 1 " "Info: 3: + IC(0.659 ns) + CELL(0.618 ns) = 2.474 ns; Loc. = LCFF_X27_Y7_N25; Fanout = 1; REG Node = 'cnt_main_part:a8254_3\|out_sgnl\[0\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.277 ns" { CLK~clkctrl cnt_main_part:a8254_3|out_sgnl[0] } "NODE_NAME" } } { "cnt_main_part.vhd" "" { Text "D:/gaochao/a8254/a8254/cnt_main_part.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.50 % ) " "Info: Total cell delay = 1.472 ns ( 59.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.002 ns ( 40.50 % ) " "Info: Total interconnect delay = 1.002 ns ( 40.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.474 ns" { CLK CLK~clkctrl cnt_main_part:a8254_3|out_sgnl[0] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "2.474 ns" { CLK {} CLK~combout {} CLK~clkctrl {} cnt_main_part:a8254_3|out_sgnl[0] {} } { 0.000ns 0.000ns 0.343ns 0.659ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "cnt_main_part.vhd" "" { Text "D:/gaochao/a8254/a8254/cnt_main_part.vhd" 52 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.168 ns + Longest register pin " "Info: + Longest register to pin delay is 3.168 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt_main_part:a8254_3\|out_sgnl\[0\] 1 REG LCFF_X27_Y7_N25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y7_N25; Fanout = 1; REG Node = 'cnt_main_part:a8254_3\|out_sgnl\[0\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_main_part:a8254_3|out_sgnl[0] } "NODE_NAME" } } { "cnt_main_part.vhd" "" { Text "D:/gaochao/a8254/a8254/cnt_main_part.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.064 ns) + CELL(2.104 ns) 3.168 ns out_sgnl\[0\] 2 PIN PIN_P7 0 " "Info: 2: + IC(1.064 ns) + CELL(2.104 ns) = 3.168 ns; Loc. = PIN_P7; Fanout = 0; PIN Node = 'out_sgnl\[0\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.168 ns" { cnt_main_part:a8254_3|out_sgnl[0] out_sgnl[0] } "NODE_NAME" } } { "a8254.vhd" "" { Text "D:/gaochao/a8254/a8254/a8254.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.104 ns ( 66.41 % ) " "Info: Total cell delay = 2.104 ns ( 66.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.064 ns ( 33.59 % ) " "Info: Total interconnect delay = 1.064 ns ( 33.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.168 ns" { cnt_main_part:a8254_3|out_sgnl[0] out_sgnl[0] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.168 ns" { cnt_main_part:a8254_3|out_sgnl[0] {} out_sgnl[0] {} } { 0.000ns 1.064ns } { 0.000ns 2.104ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.474 ns" { CLK CLK~clkctrl cnt_main_part:a8254_3|out_sgnl[0] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "2.474 ns" { CLK {} CLK~combout {} CLK~clkctrl {} cnt_main_part:a8254_3|out_sgnl[0] {} } { 0.000ns 0.000ns 0.343ns 0.659ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.168 ns" { cnt_main_part:a8254_3|out_sgnl[0] out_sgnl[0] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.168 ns" { cnt_main_part:a8254_3|out_sgnl[0] {} out_sgnl[0] {} } { 0.000ns 1.064ns } { 0.000ns 2.104ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "cnt_reg:a8254_2\|countmsb0\[5\]~reg0 data\[5\] CLK -2.396 ns register " "Info: th for register \"cnt_reg:a8254_2\|countmsb0\[5\]~reg0\" (data pin = \"data\[5\]\", clock pin = \"CLK\") is -2.396 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.484 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.484 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "a8254.vhd" "" { Text "D:/gaochao/a8254/a8254/a8254.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 122 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 122; COMB Node = 'CLK~clkctrl'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "a8254.vhd" "" { Text "D:/gaochao/a8254/a8254/a8254.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.669 ns) + CELL(0.618 ns) 2.484 ns cnt_reg:a8254_2\|countmsb0\[5\]~reg0 3 REG LCFF_X26_Y5_N23 2 " "Info: 3: + IC(0.669 ns) + CELL(0.618 ns) = 2.484 ns; Loc. = LCFF_X26_Y5_N23; Fanout = 2; REG Node = 'cnt_reg:a8254_2\|countmsb0\[5\]~reg0'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.287 ns" { CLK~clkctrl cnt_reg:a8254_2|countmsb0[5]~reg0 } "NODE_NAME" } } { "cnt_reg.vhd" "" { Text "D:/gaochao/a8254/a8254/cnt_reg.vhd" 57 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.26 % ) " "Info: Total cell delay = 1.472 ns ( 59.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.012 ns ( 40.74 % ) " "Info: Total interconnect delay = 1.012 ns ( 40.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { CLK CLK~clkctrl cnt_reg:a8254_2|countmsb0[5]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { CLK {} CLK~combout {} CLK~clkctrl {} cnt_reg:a8254_2|countmsb0[5]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" {  } { { "cnt_reg.vhd" "" { Text "D:/gaochao/a8254/a8254/cnt_reg.vhd" 57 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.029 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.029 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.772 ns) 0.772 ns data\[5\] 1 PIN PIN_AA9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.772 ns) = 0.772 ns; Loc. = PIN_AA9; Fanout = 3; PIN Node = 'data\[5\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[5] } "NODE_NAME" } } { "a8254.vhd" "" { Text "D:/gaochao/a8254/a8254/a8254.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.948 ns) + CELL(0.309 ns) 5.029 ns cnt_reg:a8254_2\|countmsb0\[5\]~reg0 2 REG LCFF_X26_Y5_N23 2 " "Info: 2: + IC(3.948 ns) + CELL(0.309 ns) = 5.029 ns; Loc. = LCFF_X26_Y5_N23; Fanout = 2; REG Node = 'cnt_reg:a8254_2\|countmsb0\[5\]~reg0'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.257 ns" { data[5] cnt_reg:a8254_2|countmsb0[5]~reg0 } "NODE_NAME" } } { "cnt_reg.vhd" "" { Text "D:/gaochao/a8254/a8254/cnt_reg.vhd" 57 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.081 ns ( 21.50 % ) " "Info: Total cell delay = 1.081 ns ( 21.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.948 ns ( 78.50 % ) " "Info: Total interconnect delay = 3.948 ns ( 78.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.029 ns" { data[5] cnt_reg:a8254_2|countmsb0[5]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "5.029 ns" { data[5] {} data[5]~combout {} cnt_reg:a8254_2|countmsb0[5]~reg0 {} } { 0.000ns 0.000ns 3.948ns } { 0.000ns 0.772ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { CLK CLK~clkctrl cnt_reg:a8254_2|countmsb0[5]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { CLK {} CLK~combout {} CLK~clkctrl {} cnt_reg:a8254_2|countmsb0[5]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.029 ns" { data[5] cnt_reg:a8254_2|countmsb0[5]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "5.029 ns" { data[5] {} data[5]~combout {} cnt_reg:a8254_2|countmsb0[5]~reg0 {} } { 0.000ns 0.000ns 3.948ns } { 0.000ns 0.772ns 0.309ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "118 " "Info: Allocated 118 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 08 18:27:27 2008 " "Info: Processing ended: Mon Sep 08 18:27:27 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}