mux_0oc.tdf

自己编写的8254计数器／计时器

--lpm_mux CASCADE_CHAIN="IGNORE" DEVICE_FAMILY="Stratix II" IGNORE_CASCADE_BUFFERS="OFF" LPM_SIZE=4 LPM_WIDTH=1 LPM_WIDTHS=2 data result sel
--VERSION_BEGIN 7.2 cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ  VERSION_END


-- Copyright (C) 1991-2007 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 1 
SUBDESIGN mux_0oc
( 
	data[3..0]	:	input;
	result[0..0]	:	output;
	sel[1..0]	:	input;
) 
VARIABLE
	l1_w0_n0_mux_dataout	:	WIRE;
	l1_w0_n1_mux_dataout	:	WIRE;
	l2_w0_n0_mux_dataout	:	WIRE;
	data_wire[5..0]	: WIRE;
	sel_wire[1..0]	: WIRE;

BEGIN 
	l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[1..1] # !(sel_wire[0..0]) & data_wire[0..0];
	l1_w0_n1_mux_dataout = sel_wire[0..0] & data_wire[3..3] # !(sel_wire[0..0]) & data_wire[2..2];
	l2_w0_n0_mux_dataout = sel_wire[1..1] & data_wire[5..5] # !(sel_wire[1..1]) & data_wire[4..4];
	data_wire[] = ( l1_w0_n1_mux_dataout, l1_w0_n0_mux_dataout, data[]);
	result[] = ( l2_w0_n0_mux_dataout);
	sel_wire[] = ( sel[1..0]);
END;
--VALID FILE