mode_set.vhd.bak

自己编写的8254计数器／计时器

  LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

-----------------------------------------------------------------
--Entity Definition
-----------------------------------------------------------------

PACKAGE  mode_set IS
    FUNCTION mode0 ( clk  : IN  std_logic;
          mode0_start :IN  std_logic;
          gate : IN  std_logic;
          CE   :IN   integer)
        return std_logic;
  FUNCTION mode1 ( clk  : IN  std_logic;
          gate : IN  std_logic;
          
    mode1_start  : IN  std_logic;
        CE : in integer) 
        return std_logic;
  FUNCTION mode2 ( clk  : IN  std_logic;
          gate : IN  std_logic;
         
          
          mode2_start  : IN  std_logic;
        CE     :in   integer) 
        return std_logic;
  FUNCTION mode3 ( clk  : IN  std_logic;
          gate : IN  std_logic;
        
          mode3_start  : IN  std_logic;
          ce: in integer) 
        return std_logic;
  FUNCTION mode4 ( 
          
          gate : IN  std_logic;
          mode4_start  : IN  std_logic;
           CE     :in   integer) 
        return std_logic;
  FUNCTION mode5 ( clk  : IN  std_logic;
          gate : IN  std_logic;
       
          
          mode5_start  : IN  std_logic;
          CE     :in   integer) 
        return std_logic;
end package  mode_set;
          
  PACKAGE BODY mode_set is
   FUNCTION mode0 ( clk  : IN  std_logic;
            mode0_start :IN std_logic;
           gate : IN  std_logic;
        
    
           CE   :IN   integer) return std_logic is
variable tmp: std_logic;
variable CEE : integer;
variable mode0_strt: std_logic; 
    begin 
     --  CEE:=0;
      --  mode0_strt:='1';
    --  if (mode0_start='1')   then
     --     mode0_strt:='0' ;
     --     while(CE>CEE) loop 
      --     if(gate='1' ) then 
      --         if(clk'event and clk='0') then 
      --        CEE:= CEE+1;
      --        tmp:='0';
      --      end if;
      --     end if;
      --   end loop; 
          tmp:='0'; ---wait until  mode0_start='1';
      --end if ;
   return  tmp;
end mode0;
  FUNCTION mode1 ( clk  : IN  std_logic;
          gate : IN  std_logic;
         
          mode1_start :in std_logic;
          CE  : IN  integer) return std_logic  is
variable tmp: std_logic;
    begin 
   tmp:='0'; 
   return  tmp;
end mode1;
  FUNCTION mode2 ( clk  : IN  std_logic;
          gate : IN  std_logic;
         
          mode2_start :in std_logic;
          CE  : IN  integer) return std_logic  is
variable tmp2: std_logic;
    begin  
  tmp2:='1';
   return  tmp2;
end mode2;
  FUNCTION mode3 ( clk  : IN  std_logic;
          gate : IN  std_logic;
         
          mode3_start :in std_logic;
          CE  : IN  integer) return std_logic is
variable tmp3: std_logic;
    begin  
   if( gate='1')
 then     tmp3:='1';
  end if;
 return  tmp3;
end mode3;
      FUNCTION mode4 (
        
          gate : IN  std_logic;
          mode4_start  : IN  std_logic;
           CE     :in   integer) return std_logic is
variable tmp4 :std_logic;
variable cee : integer  range 0 to 655536;
    begin 
 if( mode4_start='1' and gate='1') then  
     if (cee=5)  then
        
        cee:=0;
        tmp4:='0';
         else        
       cee:=cee+1;
       tmp4:='1';
         end if;
  elsif (mode4_start='1' and gate='0') then 
        cee:=0;
      tmp4:='0';
     end if;
return '1';
end function mode4;
     FUNCTION mode5 ( clk  : IN  std_logic;
          gate : IN  std_logic;
       
      mode5_start  :in std_logic;
        CE  : IN  integer) return std_logic  is
variable tmp5: std_logic;
    begin  
      tmp5:='1';
   return  tmp5;
end mode5;
END  PACKAGE BODY mode_set;



--ARCHITECTURE main OF mode4 IS

-----------------------------------------------------------------
-- Internal Architecture Signal declarations
-----------------------------------------------------------------

---SIGNAL  dout            : std_logic_vector(7 DOWNTO 0);

-----------------------------------------------------------------
-- Architecture body
-----------------------------------------------------------------
--BEGIN   

--main_proc : PROCESS(  clk,gate,WriteFinish)
--BEGIN