📄 a8254.map.rpt
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; -- 5 input functions ; 110 ;
; -- 4 input functions ; 61 ;
; -- <=3 input functions ; 156 ;
; ; ;
; Combinational ALUTs by mode ; ;
; -- normal mode ; 271 ;
; -- extended LUT mode ; 2 ;
; -- arithmetic mode ; 127 ;
; -- shared arithmetic mode ; 0 ;
; ; ;
; Estimated ALUT/register pairs used ; 509 ;
; ; ;
; Total registers ; 122 ;
; -- Dedicated logic registers ; 122 ;
; -- I/O registers ; 0 ;
; ; ;
; Estimated ALMs: partially or completely used ; 255 ;
; ; ;
; I/O pins ; 20 ;
; Maximum fan-out node ; CLK ;
; Maximum fan-out ; 122 ;
; Total fan-out ; 2038 ;
; Average fan-out ; 3.76 ;
+-----------------------------------------------+-------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+------------------------------+--------------+
; |a8254 ; 400 (0) ; 122 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 ; 0 ; |a8254 ; work ;
; |cnt_main_part:a8254_3| ; 387 (387) ; 83 (83) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |a8254|cnt_main_part:a8254_3 ; work ;
; |cnt_reg:a8254_2| ; 4 (4) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |a8254|cnt_reg:a8254_2 ; work ;
; |mode_reg:a8254_1| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |a8254|mode_reg:a8254_1 ; work ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+----------------------------------------+-------------------------------------------+
; Register name ; Reason for Removal ;
+----------------------------------------+-------------------------------------------+
; cnt_main_part:a8254_3|cee[17..31] ; Merged with cnt_main_part:a8254_3|cee[16] ;
; cnt_main_part:a8254_3|cee[16] ; Stuck at GND due to stuck port data_in ;
; cnt_main_part:a8254_3|j[0] ; Stuck at GND due to stuck port data_in ;
; mode_reg:a8254_1|wr_finish~reg0 ; Stuck at VCC due to stuck port data_in ;
; Total Number of Removed Registers = 18 ; ;
+----------------------------------------+-------------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 122 ;
; Number of registers using Synchronous Clear ; 78 ;
; Number of registers using Synchronous Load ; 31 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 97 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; cnt_main_part:a8254_3|cee[0] ; 1 ;
; Total number of inverted registers = 1 ; ;
+----------------------------------------+---------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+
; 3:1 ; 15 bits ; 30 ALUTs ; 0 ALUTs ; 30 ALUTs ; Yes ; |a8254|cnt_main_part:a8254_3|cee[9] ;
; 3:1 ; 16 bits ; 32 ALUTs ; 0 ALUTs ; 32 ALUTs ; Yes ; |a8254|cnt_reg:a8254_2|ce_0[6] ;
; 5:1 ; 8 bits ; 24 ALUTs ; 0 ALUTs ; 24 ALUTs ; Yes ; |a8254|cnt_reg:a8254_2|countlsb0[6]~reg0 ;
; 5:1 ; 8 bits ; 24 ALUTs ; 0 ALUTs ; 24 ALUTs ; Yes ; |a8254|cnt_reg:a8254_2|countmsb0[7]~reg0 ;
; 11:1 ; 31 bits ; 217 ALUTs ; 0 ALUTs ; 217 ALUTs ; Yes ; |a8254|cnt_main_part:a8254_3|j[28] ;
; 20:1 ; 16 bits ; 208 ALUTs ; 48 ALUTs ; 160 ALUTs ; Yes ; |a8254|cnt_main_part:a8254_3|i[16] ;
; 28:1 ; 15 bits ; 270 ALUTs ; 30 ALUTs ; 240 ALUTs ; Yes ; |a8254|cnt_main_part:a8254_3|i[12] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Mon Sep 08 18:50:24 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off a8254 -c a8254
Info: Found 2 design units, including 0 entities, in source file my_lib/mode_set.vhd
Info: Found design unit 1: mode_set
Info: Found design unit 2: mode_set-body
Warning: Can't analyze file -- file D:/gaochao/a8254/a8254/a8254top.vhd is missing
Info: Found 2 design units, including 1 entities, in source file cnt_main_part.vhd
Info: Found design unit 1: cnt_main_part-main
Info: Found entity 1: cnt_main_part
Info: Found 2 design units, including 1 entities, in source file cnt_reg.vhd
Info: Found design unit 1: cnt_reg-main
Info: Found entity 1: cnt_reg
Info: Found 2 design units, including 1 entities, in source file mode_reg.vhd
Info: Found design unit 1: mode_reg-main
Info: Found entity 1: mode_reg
Warning: Using design file a8254.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: a8254-main_part
Info: Found entity 1: a8254
Info: Elaborating entity "a8254" for the top level hierarchy
Info: Elaborating entity "mode_reg" for hierarchy "mode_reg:a8254_1"
Info: Elaborating entity "cnt_reg" for hierarchy "cnt_reg:a8254_2"
Info: Elaborating entity "cnt_main_part" for hierarchy "cnt_main_part:a8254_3"
Warning (10540): VHDL Signal Declaration warning at cnt_main_part.vhd(40): used explicit default value for signal "ce0" because signal was never assigned a value
Info: Duplicate registers merged to single register
Info: Duplicate register "cnt_main_part:a8254_3|cee[21]" merged to single register "cnt_main_part:a8254_3|cee[16]"
Info: Duplicate register "cnt_main_part:a8254_3|cee[28]" merged to single register "cnt_main_part:a8254_3|cee[16]"
Info: Duplicate register "cnt_main_part:a8254_3|cee[19]" merged to single register "cnt_main_part:a8254_3|cee[16]"
Info: Duplicate register "cnt_main_part:a8254_3|cee[17]" merged to single register "cnt_main_part:a8254_3|cee[16]"
Info: Duplicate register "cnt_main_part:a8254_3|cee[30]" merged to single register "cnt_main_part:a8254_3|cee[16]"
Info: Duplicate register "cnt_main_part:a8254_3|cee[22]" merged to single register "cnt_main_part:a8254_3|cee[16]"
Info: Duplicate register "cnt_main_part:a8254_3|cee[24]" merged to single register "cnt_main_part:a8254_3|cee[16]"
Info: Duplicate register "cnt_main_part:a8254_3|cee[18]" merged to single register "cnt_main_part:a8254_3|cee[16]"
Info: Duplicate register "cnt_main_part:a8254_3|cee[31]" merged to single register "cnt_main_part:a8254_3|cee[16]"
Info: Duplicate register "cnt_main_part:a8254_3|cee[20]" merged to single register "cnt_main_part:a8254_3|cee[16]"
Info: Duplicate register "cnt_main_part:a8254_3|cee[26]" merged to single register "cnt_main_part:a8254_3|cee[16]"
Info: Duplicate register "cnt_main_part:a8254_3|cee[25]" merged to single register "cnt_main_part:a8254_3|cee[16]"
Info: Duplicate register "cnt_main_part:a8254_3|cee[27]" merged to single register "cnt_main_part:a8254_3|cee[16]"
Info: Duplicate register "cnt_main_part:a8254_3|cee[23]" merged to single register "cnt_main_part:a8254_3|cee[16]"
Info: Duplicate register "cnt_main_part:a8254_3|cee[29]" merged to single register "cnt_main_part:a8254_3|cee[16]"
Warning (14130): Reduced register "cnt_main_part:a8254_3|cee[16]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "cnt_main_part:a8254_3|j[0]" with stuck data_in port to stuck value GND
Info: Power-up level of register "mode_reg:a8254_1|wr_finish~reg0" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "mode_reg:a8254_1|wr_finish~reg0" with stuck data_in port to stuck value VCC
Warning: Design contains 3 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "nRD"
Warning (15610): No output dependent on input pin "gate[1]"
Warning (15610): No output dependent on input pin "gate[2]"
Info: Implemented 468 device resources after synthesis - the final resource count might be different
Info: Implemented 17 input pins
Info: Implemented 3 output pins
Info: Implemented 448 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
Info: Allocated 164 megabytes of memory during processing
Info: Processing ended: Mon Sep 08 18:50:43 2008
Info: Elapsed time: 00:00:19
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