a8254top.map.rpt

自己编写的8254计数器／计时器

+-----------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                      ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                         ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------+
; my_lib/mode_set.vhd              ; yes             ; User VHDL File  ; D:/gaochao/LNG/a8254top/a8254top/my_lib/mode_set.vhd ;
; a8254top.vhd                     ; yes             ; Other           ; D:/gaochao/LNG/a8254top/a8254top/a8254top.vhd        ;
; mode_reg.vhd                     ; yes             ; Other           ; D:/gaochao/LNG/a8254top/a8254top/mode_reg.vhd        ;
; cnt_reg.vhd                      ; yes             ; Other           ; D:/gaochao/LNG/a8254top/a8254top/cnt_reg.vhd         ;
; cnt_main_part.vhd                ; yes             ; Other           ; D:/gaochao/LNG/a8254top/a8254top/cnt_main_part.vhd   ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------+


+------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                  ;
+-----------------------------------------------+------------------------------+
; Resource                                      ; Usage                        ;
+-----------------------------------------------+------------------------------+
; Estimated ALUTs Used                          ; 9                            ;
; Dedicated logic registers                     ; 3                            ;
;                                               ;                              ;
; Estimated ALUTs Unavailable                   ; 2                            ;
;                                               ;                              ;
; Total combinational functions                 ; 9                            ;
; Combinational ALUT usage by number of inputs  ;                              ;
;     -- 7 input functions                      ; 0                            ;
;     -- 6 input functions                      ; 3                            ;
;     -- 5 input functions                      ; 0                            ;
;     -- 4 input functions                      ; 1                            ;
;     -- <=3 input functions                    ; 5                            ;
;                                               ;                              ;
; Combinational ALUTs by mode                   ;                              ;
;     -- normal mode                            ; 9                            ;
;     -- extended LUT mode                      ; 0                            ;
;     -- arithmetic mode                        ; 0                            ;
;     -- shared arithmetic mode                 ; 0                            ;
;                                               ;                              ;
; Estimated ALUT/register pairs used            ; 11                           ;
;                                               ;                              ;
; Total registers                               ; 3                            ;
;     -- Dedicated logic registers              ; 3                            ;
;     -- I/O registers                          ; 0                            ;
;                                               ;                              ;
; Estimated ALMs:  partially or completely used ; 6                            ;
;                                               ;                              ;
; I/O pins                                      ; 20                           ;
; Maximum fan-out node                          ; mode_reg:a8254_1|main_proc~1 ;
; Maximum fan-out                               ; 5                            ;
; Total fan-out                                 ; 46                           ;
; Average fan-out                               ; 1.44                         ;
+-----------------------------------------------+------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                       ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name             ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------------------+--------------+
; |a8254top                  ; 9 (0)             ; 3 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 20   ; 0            ; |a8254top                       ; work         ;
;    |cnt_main_part:a8254_3| ; 3 (3)             ; 3 (3)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |a8254top|cnt_main_part:a8254_3 ; work         ;
;    |mode_reg:a8254_1|      ; 6 (6)             ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |a8254top|mode_reg:a8254_1      ; work         ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                                        ;
+----------------------------------------------------+------------------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal          ; Free of Timing Hazards ;
+----------------------------------------------------+------------------------------+------------------------+
; mode_reg:a8254_1|mode_choice[1]                    ; mode_reg:a8254_1|main_proc~1 ; yes                    ;
; mode_reg:a8254_1|mode_choice[2]                    ; mode_reg:a8254_1|main_proc~1 ; yes                    ;
; mode_reg:a8254_1|mode_choice[0]                    ; mode_reg:a8254_1|main_proc~1 ; yes                    ;
; mode_reg:a8254_1|cnt_choice[1]                     ; mode_reg:a8254_1|main_proc~1 ; yes                    ;
; mode_reg:a8254_1|cnt_choice[0]                     ; mode_reg:a8254_1|main_proc~1 ; yes                    ;
; Number of user-specified and inferred latches = 5  ;                              ;                        ;
+----------------------------------------------------+------------------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 3     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sun Aug 31 10:25:37 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off a8254top -c a8254top
Info: Found 2 design units, including 0 entities, in source file my_lib/mode_set.vhd
    Info: Found design unit 1: mode_set
    Info: Found design unit 2: mode_set-body
Warning: Using design file a8254top.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: a8254top-main_part
    Info: Found entity 1: a8254top
Info: Elaborating entity "a8254top" for the top level hierarchy
Warning: Using design file mode_reg.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: mode_reg-main
    Info: Found entity 1: mode_reg
Info: Elaborating entity "mode_reg" for hierarchy "mode_reg:a8254_1"
Warning (10631): VHDL Process Statement warning at mode_reg.vhd(37): inferring latch(es) for signal or variable "cnt_choice", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at mode_reg.vhd(37): inferring latch(es) for signal or variable "rwmode", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at mode_reg.vhd(37): inferring latch(es) for signal or variable "mode_choice", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at mode_reg.vhd(37): inferring latch(es) for signal or variable "binnbcd", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "binnbcd" at mode_reg.vhd(37)
Info (10041): Inferred latch for "mode_choice[0]" at mode_reg.vhd(37)
Info (10041): Inferred latch for "mode_choice[1]" at mode_reg.vhd(37)
Info (10041): Inferred latch for "mode_choice[2]" at mode_reg.vhd(37)
Info (10041): Inferred latch for "rwmode[0]" at mode_reg.vhd(37)
Info (10041): Inferred latch for "rwmode[1]" at mode_reg.vhd(37)