a8254top.vhd.bak

自己编写的8254计数器／计时器

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

-----------------------------------------------------------------
--Entity Definition
-----------------------------------------------------------------

ENTITY a8254 IS
    PORT (
        nCS          : IN     std_logic;												 
        nWR          : IN     std_logic;						  
        nRD          : IN     std_logic;						  
        gate         : IN     std_logic_vector(2 downto 0);						  
       	CLK			 : in        std_logic;  
        data         : in      std_logic_vector( 7 downto 0);
        adrs         : in      std_logic_vector(1 downto 0);  ---decide the address to read or write together with nCS

                
       out_sgnl      : OUT    std_logic_vector(2 DOWNTO 0)	  
     				  
        );
END;

-----------------------------------------------------------------
--ARCHITECTURE Definition
-----------------------------------------------------------------

ARCHITECTURE main_part OF a8254 IS

-----------------------------------------------------------------
-- COMPONENT Declarations
-----------------------------------------------------------------

COMPONENT mode_reg 
   PORT ( clk    : in  std_logic;
          nCS    : IN  std_logic;
          adrs   : IN  std_logic_vector(1 DOWNTO 0);
          nWR    : IN  std_logic;
          nRD    : IN  std_logic;
          data   : in      std_logic_vector( 7 downto 0);
          
          wr_finish : out std_logic;
          rwmode    : OUT std_logic_vector(1 DOWNTO 0);
        mode_choice : out std_logic_vector(2 downto 0);
        cnt_choice  : out  std_logic_vector(1 downto 0);
         binnbcd    : out   std_logic
       
        );

END COMPONENT;



COMPONENT cnt_main_part
     PORT (
           gate       :   in  std_logic_vector(2 downto 0);
            clk        :   in   std_logic;
            adrs   : in std_logic_vector( 1 downto 0);
            nCS    : in std_logic;
            nWR    : IN  std_logic;
            data   : IN  std_logic_vector(7 DOWNTO 0);
        
             rwmode  : IN  std_logic_vector(1 DOWNTO 0);
         mode_choice : IN  std_logic_vector(2 DOWNTO 0);
          cnt_choice : IN  std_logic_vector(1 DOWNTO 0);
          binnbcd    : IN  std_logic;
          wr_finish  : in std_logic;
          
        
           out_sgnl   : OUT std_logic_vector(2 DOWNTO 0));
	  
     				  

END COMPONENT;

-----------------------------------------------------------------
-- SIGNAL Declarations
-----------------------------------------------------------------

 signal      rwmode       :  std_logic_vector(1 DOWNTO 0);
 signal      mode_choice  :  std_logic_vector(2 downto 0);
 signal       cnt_choice  :   std_logic_vector(1 downto 0);
 signal        binnbcd    :    std_logic;
signal        wr_finish    :  std_logic;
-----------------------------------------------------------------
-- Architecture Body
-----------------------------------------------------------------
BEGIN

	-- Rename some  of the control register outputs
 
     
	-- Instaniate Read/Write Control module
   a8254_1 : mode_reg
    PORT MAP(clk=>clk,
        nCS  => nCS,    					
        adrs  => adrs,      					 
        nWR  => nWR,    				  
        nRD  => nRD,       				 
        data =>  data,        					 
       	wr_finish => wr_finish,			
        rwmode =>rwmode,
       mode_choice =>mode_choice,
       cnt_choice =>cnt_choice,
       binnbcd =>binnbcd
     );
  a8254_2 :cnt_main_part
    PORT MAP(
    gate=>gate ,     
          clk=>clk , 
          adrs=>adrs,
         nCS=>nCS,
        nWR=>nWR,
        data=>data,
        rwmode=>rwmode,
    ,  mode_choice=>mode_choice,
          cnt_choice=>cnt_choice ,
          binnbcd=>binnbcd,   
     wr_finish=> wr_finish ,
      out_sgnl=>out_sgnl );
 END main_part;