despread.v

Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH

//Module FA_1B For CSA
module FA_1B(Carry_Out, SUM, A, B, C);
output 	SUM, Carry_Out;
input  	A, B, C;
wire   	AB, AC, BC;

//gate #(rise_delay (min:typ:max), fall_delay(min:typ:max) )

xor  #(0.6:0.8:1.1, 0.6:0.8:1.1 ) u2( SUM, A, B, C);

nand #(0.3:0.5:0.7, 0.3:0.5:0.7 ) u3( AB, A, B );
nand #(0.3:0.5:0.7, 0.3:0.5:0.7 ) u4( AC, A, C );
nand #(0.3:0.5:0.7, 0.3:0.5:0.7 ) u5( BC, B, C );
nand #(0.4:0.6:0.8, 0.4:0.6:0.8 ) u6( Carry_Out, AB, AC, BC );
endmodule 

module CSA_8B( C_OUT, SUM, A, B, C );

output  [7:0] C_OUT;
output  [7:0] SUM; 
input   [7:0] A;
input   [7:0] B;
input   [7:0] C;

wire [7:0] SUM;
wire [7:0] C_TEMP;
wire [7:0] C_OUT;

FA_1B fa1( C_TEMP[0], SUM[0], A[0], B[0], C[0] ); 
FA_1B fa2( C_TEMP[1], SUM[1], A[1], B[1], C[1] ); 
FA_1B fa3( C_TEMP[2], SUM[2], A[2], B[2], C[2] ); 
FA_1B fa4( C_TEMP[3], SUM[3], A[3], B[3], C[3] ); 
FA_1B fa5( C_TEMP[4], SUM[4], A[4], B[4], C[4] ); 
FA_1B fa6( C_TEMP[5], SUM[5], A[5], B[5], C[5] ); 
FA_1B fa7( C_TEMP[6], SUM[6], A[6], B[6], C[6] ); 
FA_1B fa8( C_TEMP[7], SUM[7], A[7], B[7], C[7] ); 

assign C_OUT[7:0]={C_TEMP[6:0],1'b0};
endmodule



module CSA_BLOCK( C_OUT, SUM, A, B, C, D, E, F, G, H, I, J, K );

output [7:0] C_OUT,SUM;
input  [3:0] A, B, C, D, E, F, G, H, I, J, K;

wire   [7:0] C_OUT,SUM;

wire   [7:0] sA, sB, sC, sD, sE, sF, sG, sH, sI, sJ, sK;
wire   [7:0] nB, nE, nI, nJ, nK;
wire   [7:0] S1, S2, S3, S4, S5, S6, S7, S8 ,S9; 
wire   [7:0] C1, C2, C3, C4, C5, C6, C7, C8 ,C9;

assign sA[7:0]={A[3],A[3],A[3],A[3],A[3:0]};
assign sB[7:0]={B[3],B[3],B[3],B[3],B[3:0]};
assign sC[7:0]={C[3],C[3],C[3],C[3],C[3:0]};
assign sD[7:0]={D[3],D[3],D[3],D[3],D[3:0]};
assign sE[7:0]={E[3],E[3],E[3],E[3],E[3:0]};

assign sF[7:0]={F[3],F[3],F[3],F[3],F[3:0]};
assign sG[7:0]={G[3],G[3],G[3],G[3],G[3:0]};
assign sH[7:0]={H[3],H[3],H[3],H[3],H[3:0]};
assign sI[7:0]={I[3],I[3],I[3],I[3],I[3:0]};
assign sJ[7:0]={J[3],J[3],J[3],J[3],J[3:0]};

assign sK[7:0]={K[3],K[3],K[3],K[3],K[3:0]};
 
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) n1( nB[0], sB[0] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) n2( nB[1], sB[1] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) n3( nB[2], sB[2] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) n4( nB[3], sB[3] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) n5( nB[4], sB[4] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) n6( nB[5], sB[5] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) n7( nB[6], sB[6] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) n8( nB[7], sB[7] );

not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) m1( nE[0], sE[0] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) m2( nE[1], sE[1] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) m3( nE[2], sE[2] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) m4( nE[3], sE[3] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) m5( nE[4], sE[4] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) m6( nE[5], sE[5] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) m7( nE[6], sE[6] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) m8( nE[7], sE[7] );

not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) o1( nI[0], sI[0] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) o2( nI[1], sI[1] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) o3( nI[2], sI[2] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) o4( nI[3], sI[3] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) o5( nI[4], sI[4] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) o6( nI[5], sI[5] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) o7( nI[6], sI[6] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) o8( nI[7], sI[7] );


not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) p1( nJ[0], sJ[0] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) p2( nJ[1], sJ[1] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) p3( nJ[2], sJ[2] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) p4( nJ[3], sJ[3] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) p5( nJ[4], sJ[4] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) p6( nJ[5], sJ[5] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) p7( nJ[6], sJ[6] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) p8( nJ[7], sJ[7] );

not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) q1( nK[0], sK[0] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) q2( nK[1], sK[1] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) q3( nK[2], sK[2] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) q4( nK[3], sK[3] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) q5( nK[4], sK[4] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) q6( nK[5], sK[5] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) q7( nK[6], sK[6] );
not #(0.2:0.3:0.5, 0.2:0.3:0.5 ) q8( nK[7], sK[7] );  
 
CSA_8B csa1(C1, S1, sA, sC, sD);
CSA_8B csa2(C2, S2, sF, sG, sH);

CSA_8B csa3(C3, S3, C1, S1, C2);
CSA_8B csa4(C4, S4, S2, C3, S3);

CSA_8B csa5(C5, S5, nB, nE, 8'd5);
CSA_8B csa6(C6, S6, nI, nJ, nK);

CSA_8B csa7(C7, S7, S5, C5, C6);
CSA_8B csa8(C8, S8, S6, S7, C7);

CSA_8B csa9 (C9,  S9,  S4, C4, C8);
CSA_8B csa10(C_OUT, SUM, S8, S9, C9);
endmodule


module KS_8B(OUT, A, B);
output [7:0] OUT;
input  [7:0] A, B;

wire P0, P1, P2, P3, P4, P5, P6, P7;
wire G0, G1, G2, G3, G4, G5, G6, G7;

wire T1, T2, T3, T4, T5, T6, T7;
wire T21, T22, T23, T24, T25, T26;
wire T31, T32, T33, T34;

wire nG0, nG1, nG2, nG3, nG4, nG5, nG6, nG7;

wire G21, G32, G43, G54, G65, G76;
wire P21, P32, P43, P54, P65, P76;
wire nG21, nG32, nG43, nG54,nG65,nG76;

wire G41, G52, G63, G74;
wire P41, P52, P63, P74;
wire nG41, nG52, nG63, nG74;



xor  #(0.5:0.7:1.0, 0.5:0.7:1.0 ) p0(P0, A[0], B[0] );
xor  #(0.5:0.7:1.0, 0.5:0.7:1.0 ) p1(P1, A[1], B[1] );
xor  #(0.5:0.7:1.0, 0.5:0.7:1.0 ) p2(P2, A[2], B[2] );
xor  #(0.5:0.7:1.0, 0.5:0.7:1.0 ) p3(P3, A[3], B[3] );
xor  #(0.5:0.7:1.0, 0.5:0.7:1.0 ) p4(P4, A[4], B[4] );
xor  #(0.5:0.7:1.0, 0.5:0.7:1.0 ) p5(P5, A[5], B[5] );
xor  #(0.5:0.7:1.0, 0.5:0.7:1.0 ) p6(P6, A[6], B[6] );
xor  #(0.5:0.7:1.0, 0.5:0.7:1.0 ) p7(P7, A[7], B[7] );


and  #(0.4:0.6:0.9, 0.4:0.6:0.9 ) g0(G0, A[0], B[0] );
and  #(0.4:0.6:0.9, 0.4:0.6:0.9 ) g1(G1, A[1], B[1] );
and  #(0.4:0.6:0.9, 0.4:0.6:0.9 ) g2(G2, A[2], B[2] );
and  #(0.4:0.6:0.9, 0.4:0.6:0.9 ) g3(G3, A[3], B[3] );
and  #(0.4:0.6:0.9, 0.4:0.6:0.9 ) g4(G4, A[4], B[4] );
and  #(0.4:0.6:0.9, 0.4:0.6:0.9 ) g5(G5, A[5], B[5] );
and  #(0.4:0.6:0.9, 0.4:0.6:0.9 ) g6(G6, A[6], B[6] );
and  #(0.4:0.6:0.9, 0.4:0.6:0.9 ) g7(G7, A[7], B[7] );

not  #(0.2:0.3:0.5, 0.2:0.3:0.5 )  n0(nG0, G0);
not  #(0.2:0.3:0.5, 0.2:0.3:0.5 )  n1(nG1, G1);
not  #(0.2:0.3:0.5, 0.2:0.3:0.5 )  n2(nG2, G2);
not  #(0.2:0.3:0.5, 0.2:0.3:0.5 )  n3(nG3, G3);
not  #(0.2:0.3:0.5, 0.2:0.3:0.5 )  n4(nG4, G4);
not  #(0.2:0.3:0.5, 0.2:0.3:0.5 )  n5(nG5, G5);
not  #(0.2:0.3:0.5, 0.2:0.3:0.5 )  n6(nG6, G6);
not  #(0.2:0.3:0.5, 0.2:0.3:0.5 )  n7(nG7, G7);

not  #(0.2:0.3:0.5, 0.2:0.3:0.5 )  n17(nG21, G21);
not  #(0.2:0.3:0.5, 0.2:0.3:0.5 )  n8(nG32, G32);

not  #(0.2:0.3:0.5, 0.2:0.3:0.5 )   n9(nG43, G43);
not  #(0.2:0.3:0.5, 0.2:0.3:0.5 )  n10(nG54, G54);
not  #(0.2:0.3:0.5, 0.2:0.3:0.5 )  n11(nG65, G65);
not  #(0.2:0.3:0.5, 0.2:0.3:0.5 )  n12(nG76, G76);

not  #(0.2:0.3:0.5, 0.2:0.3:0.5 )  n13(nG41, G41);
not  #(0.2:0.3:0.5, 0.2:0.3:0.5 )  n14(nG52, G52);
not  #(0.2:0.3:0.5, 0.2:0.3:0.5 )  n15(nG63, G63);
not  #(0.2:0.3:0.5, 0.2:0.3:0.5 )  n16(nG74, G74);

nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (T1, G0, P1  );
nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (C1, T1, nG1 );

nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (T2 , G1, P2  );
nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (G21, T2, nG2 );
and  #(0.4:0.6:0.9, 0.4:0.6:0.9 )  (P21, P1, P2  ); 

nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (T3 , G2, P3  );
nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (G32, T3, nG3 );
and  #(0.4:0.6:0.9, 0.4:0.6:0.9 )  (P32, P2, P3  ); 

nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (T4 , G3, P4  );
nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (G43, T4, nG4 );
and  #(0.4:0.6:0.9, 0.4:0.6:0.9 )  (P43, P3, P4  ); 

nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (T5 , G4, P5  );
nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (G54, T5, nG5 );
and  #(0.4:0.6:0.9, 0.4:0.6:0.9 )  (P54, P4, P5  ); 

nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (T6 , G5, P6  );
nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (G65, T6, nG6 );
and  #(0.4:0.6:0.9, 0.4:0.6:0.9 )  (P65, P5, P6  ); 

nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (T7 , G6, P7  );
nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (G76, T7, nG7 );
and  #(0.4:0.6:0.9, 0.4:0.6:0.9 )  (P76, P6, P7  ); 

//****************************************************************
nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (T21, G0, P21  );
nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (C2, T21, nG21 ); 

nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (T22, C1, P32  );
nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (C3, T22, nG32 );

nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (T23, P43, G21  );
nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (G41, T23, nG43 );
and  #(0.4:0.6:0.9, 0.4:0.6:0.9 )  (P41 , P21, P43  ); 

nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (T24, P54, G32  );
nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (G52, T24, nG54 );
and  #(0.4:0.6:0.9, 0.4:0.6:0.9 )  (P52, P32, P54  ); 

nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (T25 , P65, G43 );
nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (G63, T25, nG65  );
and  #(0.4:0.6:0.9, 0.4:0.6:0.9 )  (P63, P43, P65  ); 

nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (T26 , P76, G54 );
nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (G74, T26, nG76  );
and  #(0.4:0.6:0.9, 0.4:0.6:0.9 )  (P74, P54, P76  ); 

//*****************************************************************

nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (T31, G0, P41  );
nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (C4, T31, nG41 );

nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (T32, C1, P52  );
nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (C5, T32, nG52 );

nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (T33, C2, P63  );
nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (C6, T33, nG63 );

nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (T34, C3, P74  );
nand #(0.3:0.5:0.7, 0.3:0.5:0.7 )  (C7, T34, nG74 );


assign OUT[0]=P0;

xor #(0.5:0.7:1.0, 0.5:0.7:1.0 ) out1(OUT[1],G0,P1);
xor #(0.5:0.7:1.0, 0.5:0.7:1.0 ) out2(OUT[2],C1,P2);
xor #(0.5:0.7:1.0, 0.5:0.7:1.0 ) out3(OUT[3],C2,P3);
xor #(0.5:0.7:1.0, 0.5:0.7:1.0 ) out4(OUT[4],C3,P4);
xor #(0.5:0.7:1.0, 0.5:0.7:1.0 ) out5(OUT[5],C4,P5);
xor #(0.5:0.7:1.0, 0.5:0.7:1.0 ) out6(OUT[6],C5,P6);

xor #(0.5:0.7:1.0, 0.5:0.7:1.0 ) out7(OUT[7],C6,P7);

endmodule





module DESPREAD(OUT, A, B, C, D, E, F, G, H, I, J, K );
output [7:0] OUT;
input  [3:0] A, B, C, D, E, F, G, H, I, J, K;
wire   [7:0] C_OUT,SUM;

CSA_BLOCK a( C_OUT, SUM, A, B, C, D, E, F, G, H, I, J, K );
KS_8B     b( OUT, C_OUT, SUM);
endmodule