mmx_chp4.htm

MMX即多媒体可扩展指令集

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<a name="Figure4-2"></a>
<CENTER><IMG SRC="3006046.gif" tppabs="http://freemind.163.net/database/mmx/3006046.gif" border=0></CENTER><br>

<CENTER><small>Figure 4-2. Aliasing of MMX&#153; Technology to Floating-Point Registers</small></CENTER><br>

MMX registers map to the physical locations of floating-point registers. MMX register mapping is fixed and does not change when the TOS (Top Of Stack field in the floating-point status word, bits 11-13) changes.<br><br>

The value of the TOS is set to 0 after each MMX instruction.<br><br>

In the floating-point context, STn refers to the relative location of a FP register, n, to the TOS. However, the FP tag bits refer to the physical locations of the FP register. The MMX registers always refer to the physical location.<br><br>

In Figure 4-3, the inner circle refers to the physical location of the FP and MMX&#153; registers. The outer circle refers to FP register's relative location to the current TOS.<br><br>

When the TOS=0 (case a in Figure&nbsp;4&#173;3), ST0 points to the physical location 0 on the floating-point stack. MM0 maps to ST0, MM1 maps to ST1, and so on.<br><br>

When the TOS=2 (case b in Figure&nbsp;4&#173;3), ST0 points to the physical location 2. MM0 maps to ST6, MM1 maps to ST7, MM2 maps to ST0, and so on.<br><br>

<a name="Figure4-3"></a>
<CENTER><IMG SRC="3006006.gif" tppabs="http://freemind.163.net/database/mmx/3006006.gif" border=0></CENTER><br>

<CENTER><small>Figure 4-3. Mapping of MMX&#153; Registers to Floating Point Registers</small></CENTER>

<H4><a name="4.3.2">4.3.2 The Effect of Floating-Point and MMX&#153; Instructions on the Floating-Point Tag Word</a></H4>

Using an MMX instruction (except EMMS) validates (sets to 00s) the entire floating-point tag word.<br><br>

The EMMS instruction sets the entire FP tag bits register to empty (11s in each tag field).<br><br>

FSAVE and FSTENV instructions read the FP tag word and store the contents of the FP tag word in memory. Executing these instructions calculates the precise values of the FP tag word fields based on the current contents of the registers.  After executing these instructions, all tag bit values are valid for MMX instructions: Valid, Zero, Special, Empty.  The value of the FP tag word does not affect the MMX registers or execution of MMX instructions.<br><br>

Table 4-1 summarizes the effect of FP or MMX instructions and FSAVE/ FSTENV instructions on the tag bit fields in an FP or MMX register and defines their value in memory.<br><br>

<a name="Table4-1"></a>
<center><table border="0" cellpadding="2" cellspacing="1" bgcolor="#EBDABE">
<TR><TD bgcolor="#000000" COLSPAN=4 WIDTH=524 align=center><small><b>Table 4-1. Effect of the FP and MMX&#153; Instructions on the FP Tag Word</b></small></TD></TR>

<TR><TD bgcolor="#000000" WIDTH=121><CENTER><small><B>Instruction Type</B></small></CENTER></TD><TD bgcolor="#000000" WIDTH=134><CENTER><small><B>Instruction</B></small></CENTER></TD><TD bgcolor="#000000" WIDTH=134><CENTER><small><B>Tag Bits</B></small></CENTER></TD><TD bgcolor="#000000" WIDTH=134><CENTER><small><B>Calculated FP Tag Word in Memory After FSAVE/FSTENV</B></small></CENTER></TD></TR>

<TR><TD bgcolor="#000000" WIDTH=121><FONT SIZE=1 COLOR=#000000>MMX&#153;</small></TD><TD bgcolor="#000000" WIDTH=134><small>All (except EMMS)</small></TD><TD bgcolor="#000000" WIDTH=134><small>All registers' tags are set to zeros (00).</small></TD><TD bgcolor="#000000" WIDTH=134><small>00, 01, 10</small></TD></TR>

<TR><TD bgcolor="#000000" WIDTH=121><FONT SIZE=1 COLOR=#000000>MMX</small></TD><TD bgcolor="#000000" WIDTH=134><small>EMMS</small></TD><TD bgcolor="#000000" WIDTH=134><small>All registers' tags are set to ones (11).</small></TD><TD bgcolor="#000000" WIDTH=134><small>11</small></TD></TR>

<TR><TD bgcolor="#000000" WIDTH=121><small>FP</small></TD><TD bgcolor="#000000" WIDTH=134><small>All (except FRSTOR, FLDENV)</small></TD><TD bgcolor="#000000" WIDTH=134><small>Individual register tag is set to 00 or 11.</small></TD><TD bgcolor="#000000" WIDTH=134><small>Each register's tags are set to 00, 11, 01 or 10.</small></TD></TR>

<TR><TD bgcolor="#000000" WIDTH=121><small>FP</small></TD><TD bgcolor="#000000" WIDTH=134><small>FRSTOR, FLDENV</small></TD><TD bgcolor="#000000" WIDTH=134><small>All registers' tags are set to 00 or 11 or 01 or 10.</small></TD><TD bgcolor="#000000" WIDTH=134><small>Each register's tags are set to 00, 11, 01 or 10.</small></TD></TR>
</table></center><br>

<b><a name="4.3.2.1">4.3.2.1 ALIASING SUMMARY</a></b><br><br>

Table 4-2 summarizes the effects of the MMX&#153; instructions on the floating-point state.<br><br>

<a name="Table4-2"></a>
<center><table border="0" cellpadding="2" cellspacing="1" bgcolor="#EBDABE">
<TR><TD bgcolor="#000000" COLSPAN=6 WIDTH=509 align=center><small><b>Table 4-2. Effects of MMX&#153; Instruction on FP State</small></A></b></small></TD></TR>

<TR><TD bgcolor="#000000" WIDTH=85><CENTER><small><B>Instruction Type</B></small></CENTER></TD><TD bgcolor="#000000" WIDTH=85><CENTER><small><B>FP Tag Word</B></small></CENTER></TD><TD bgcolor="#000000" WIDTH=76><CENTER><small><B>TOS (SW13..11)</B></small></CENTER></TD><TD bgcolor="#000000" WIDTH=88><CENTER><small><B>Other FP Environment (CW, Data Ptr, Code Ptr, Other Fields)</B></small></CENTER></TD><TD bgcolor="#000000" WIDTH=88><CENTER><small><B>Exponent Bits + Signed Bit of MMn (79..64)</B></small></CENTER></TD><TD bgcolor="#000000" WIDTH=88><CENTER><small><B>Mantissa Part of MMn (63..00)</B></small></CENTER></TD></TR>

<TR><TD bgcolor="#000000" WIDTH=85><small>MMX register read from MMX register (MMn)</small></TD><TD bgcolor="#000000" WIDTH=85><small>All fields set to 00 (Valid)</small></TD><TD bgcolor="#000000" WIDTH=76><small>000</small></TD><TD bgcolor="#000000" WIDTH=88><small>Unchanged</small></TD><TD bgcolor="#000000" WIDTH=88><small>Unchanged</small></TD><TD bgcolor="#000000" WIDTH=88><small>Unchanged</small></TD></TR>

<TR><TD bgcolor="#000000" WIDTH=85><small>MMX register write to MMX register (MMn)</small></TD><TD bgcolor="#000000" WIDTH=85><small>All fields set to 00 (Valid)</small></TD><TD bgcolor="#000000" WIDTH=76><small>000</small></TD><TD bgcolor="#000000" WIDTH=88><small>Unchanged</small></TD><TD bgcolor="#000000" WIDTH=88><small>Set to ones (11)</small></TD><TD bgcolor="#000000" WIDTH=88><small>Overwritten</small></TD></TR>

<TR><TD bgcolor="#000000" WIDTH=85><small>EMMS</small></TD><TD bgcolor="#000000" WIDTH=85><small>All fields set to 11 (Empty)</small></TD><TD bgcolor="#000000" WIDTH=76><small>000</small></TD><TD bgcolor="#000000" WIDTH=88><small>Unchanged</small></TD><TD bgcolor="#000000" WIDTH=88><small>Unchanged</small></TD><TD bgcolor="#000000" WIDTH=88><small>Unchanged</small></TD></TR>
</table></center>

<br>
<small>Note: MMn refers to one MMX register.</small>

<H4><a name="4.3.3">4.3.3 Context Switch Support</a></H4>

If the task switch bit (TS) in control register 0 (CR0) is set (CR0.TS=1), the first FP or MMX instruction that executes will trigger Int 7, Device not available (DNA). Causing a DNA fault enables an operating system to save the context of the FP or MMX registers with the same code currently used to save the FP state. Both the FSAVE (Store FP state) and FRSTOR (Restore FP state) instructions are used to save and restore either the FP or MMX state.<br><br>

See Section <A NAME="HOME">X_ContextSwitching 4.1. for more details on context switching.</A>

<H4><a name="4.3.4">4.3.4 Floating-Point Exceptions</a></H4>

When floating-point exceptions are enabled and a FP exception is pending, subsequent MMX instruction execution reports an FP error (Int 16 and/or FERR# signal). The pending exception is handled by the FP exception handler. Execution resumes at the interrupted MMX instruction.<br><br>

Before the MMX instruction is executed, the FP state is maintained and is visible to the FP exception handler.<br><br>

See Section 3.3.6 for more detail.

<H4><a name="4.3.5">4.3.5 Debugging</a></H4>

The debug features for Intel Architecture implementations operate in the same manner on the MMX instruction set. This enables debuggers to debug code that uses the MMX technology.

<H4><a name="4.3.6">4.3.6 Emulation of the Instruction Set</a></H4>

There is no emulation support for microprocessors that support the MMX technology.<br><br>

The CR0.EM bit used to emulate floating-point instructions cannot be used in the same way for MMX instruction emulation. If an MMX instruction executes when the CR0.EM bit is set, an invalid opcode exception (Int 6) is generated.

<H4><a name="4.3.7">4.3.7 Exception handling in Operating Systems</a></H4>

This section specifies system exceptions. Exception handling in MMX code is discussed in Section 3.3.6.<br><br>

An invalid opcode exception (Int 6)  can occur due to MMX instruction execution two cases:

<ul>
<li>On implementations that do not support IA MMX technology.
<li>When CR0.EM=1 and an MMX instruction is executed.
</ul>

The CR0.EM bit is used to emulate the FP instructions in software. In this case, the operating system does not save the FP hardware state on task switches and does not save the MMX state.  An invalid opcode exception is generated to flag this event to the operating system, and prevent application errors from occurring.

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