📄 mmx_chp4.htm
字号:
<html>
<head>
<meta content="charset=gb2312">
</head>
<style type="text/css">
<!--
p,td,body {font: 10.5pt}
small {font: 9pt;}
big {font: 24pt}
h1 {font: 22pt}
h2 {font: 20pt}
h3 {font: 18pt}
h4 {font: 16pt}
h5 {font: 14pt}
h6 {font: 12pt}
A:link {text-decoration: none; color: "#DBCAAE"}
A:visited {text-decoration: none; color: "#DBCAAE"}
A:active {text-decoration: none; color: "#DBCAAE"}
A:hover {text-decoration: none; color: "#FBEACE"}
-->
</style>
<body bgcolor="#000000" text="#DBCAAE" link="#DBCAAE" vlink="#DBCAAE" alink="#DBCAAE" topmargin="10" leftmargin="4">
<p>
<center>
<a href="tppmsgs/msgs0.htm#1" tppabs="http://freemind.163.net/index.html"><img src="bigtitle.gif" tppabs="http://freemind.163.net/bigtitle.gif" width=505 height=92 border="0"></a><br>
</center>
<big><FONT FACE="Arial"><B><FONT COLOR="#FBEACE">D</FONT><FONT COLOR="#EBDABE">A</FONT><FONT COLOR="#DBCAAE">T</FONT><FONT COLOR="#CBBA9E">A</FONT><FONT COLOR="#BBAA8E">B</FONT><FONT COLOR="#AB9A7E">A</FONT><FONT COLOR="#9B8A6E">S</FONT><FONT COLOR="#8B7A5E">E</FONT></B></FONT></big>
<table border="0" cellpadding="0" cellspacing="0" width="100%"><tr><td bgcolor="#CBBA9E" height="1"></td></tr><tr><td bgcolor="#FBEACE" height="1"></td></tr><tr><td bgcolor="#DBCAAE" height="1"></td></tr><tr><td bgcolor="#BBAA8E" height="1"></td></tr><tr><td bgcolor="#9B8A6E" height="1"></td></tr><tr><td bgcolor="#7B6A4E" height="1"></td></tr><tr><td bgcolor="#5B4A2E" height="1"></td></tr><tr><td bgcolor="#3B2A0E" height="1"></td></tr><tr><td height="10"></td></tr></table>
<center>
<big><font face="黑体">INTEL 体系结构<br>MMX™ 技术程序员参考手册</font></big><br>
<small><FONT FACE="Arial"><b>Intel Architecture MMX™ Technology Programmer's Reference Manual</b></font></small><br><br>
</center>
<table border="0" width="100%" border="0" cellpadding="2" cellspacing="0"><tr><TD bgcolor="#000000" align="right"><a href="mmx.htm" tppabs="http://freemind.163.net/database/mmx/mmx.htm">返回</a></td></tr></table>
<table border="0" width="100%"><tr><td bgcolor="#CBBA9E" height="2"></td></tr></table>
</p>
<p><font face="arial">
<h3><b>Chapter 4<BR>SYSTEM PROGRAMMING MODEL</b></h3>
This chapter presents the interface of the Intel Architecture MMX™ technology to the operating system.
<H3><a name="4.1">4.1 CONTEXT SWITCHING</a></H3>
This section describes the behavior of operating systems during context switching.<br><br>
Different operating systems take different approaches for state-saving:
<ul>
<li> Some operating systems save the entire floating-point state.
<li> Some save the floating-point state only when it is required.
<li> Some may save a partial floating-point state.
</ul>
The existing task switch code for IA implementations (including floating-point code) does not change for systems that include MMX code.
<H4><a name="4.1.1">4.1.1 Cooperative Multitasking Operating System</a></H4>
In a cooperative operating system, application tasks can predetermine when it is about to be switched out. Tasks can prepare in advance for the switch.<br><br>
Application programmers must know whether the operating system performs a state save or whether it is their responsibility to perform a state save.
<H4><a name="4.1.2">4.1.2 Preemptive Multitasking Operating System</a></H4>
In a preemptive multitasking operating system, the application cannot know when it is preempted. Applications cannot prepare in advance for task switching. The operating system is responsible for saving and restoring the state when necessary.<br><br>
The IA MMX technology was defined to support the same state-saving and restoring techniques as the floating-point state-saving and restoring techniques. Existing operating systems can continue to run without modifications.<br><br>
Figure 4-1 illustrates an example of an operating system implementing floating-point or MMX state saving.<br><br>
Detecting when to save the FP or MMX state needs to be saved is the same process used for detecting when the floating-point state needs to be saved. If CR0.TS=1 (task switch bit in control register 0), then the next FP or MMX instruction generates exception Int 7.
<OL>
<LI>The operating system maintains a <I>save area</I> for each task (Save Areas A and B in Figure 4­1).
<LI>It defines a variable that indicates which task "owns" the FP or MMX state.
<LI>On a task switch, the OS sets the CR0.TS to 1 if the incoming task does not own the FP or MMX state. Otherwise, it sets it to 0.
<LI>If a new task attempts to use an MMX instruction, (while CR0.TS=1), exception Int 7 is generated. The Int 7 handler ("owned" by the operating system) saves the FP or MMX state to the save area of the FP or MMX state owner and restores the FP or MMX state from the save area of the current task.
<LI>The ownership of the FP or MMX state then changes to the current task and CR0.TS=0.
</OL>
<a name="Figure4-1"></a>
<CENTER><IMG SRC="3006008.gif" tppabs="http://freemind.163.net/database/mmx/3006008.gif" border=0></CENTER><br>
<CENTER><small>Figure 4-1. Example of FP and MMX<sup>TM</sup> Technology State Saving in Operating System</small></CENTER>
<H3><a name="4.2">4.2 EXCEPTIONS</a></H3>
MMX instructions do not generate numeric exceptions or affect the processor architecture status flags. Previously pending floating-point numeric errors are reported.<br><br>
The MMX instructions can generate the following exceptions:
<ul>
<li> Memory access exceptions:<br>#SS Interrupt 12 - Stack exception<br>#GP Interrupt 13 - General Protection<br>#PF Interrupt 14 - Page Fault<br>#AC Interrupt 17 - Alignment Check, if enabled by CPU configuration.
<li> System exceptions:<br>#UD Interrupt 6 - Invalid Opcode<br> Executing an MMX instruction when CR0.EM=1 generates an Invalid Opcode exception.<br>#NM Interrupt 7 - Device not available. The TS bit in CR0 is set.
<li> Pending floating-point error:<br>#MF Interrupt 16 - Pending floating-point error
<li> Other exceptions that occur indirectly due to faulty execution of the above exceptions. For example: Interrupt 12 occurs due to MMX instructions, and the interrupt gate directs the processor to invalid TSS (task state segment).
</ul>
The MMX instructions are accessible from all operation modes of IA: Protected mode, Real address mode, and Virtual 8086 mode.
<H3><a name="4.3">4.3 COMPATIBILITY WITH EXISTING SOFTWARE ENVIRONMENTS</a></H3>
<H4><a name="4.3.1">4.3.1 Register Aliasing</a></H4>
The MMX state is aliased on the floating-point state:
<ul>
<li>MMX registers MM0-MM7 are aliased on the 64-bit mantissas of the floating-point register (See Figure 4-2).
<li>A value written to an MMX register using MMX instructions also appears in one of the eight floating-point registers (bits 63-0). The exponent field of the corresponding floating-point register (bits 78-64) and its sign bit (bit 79) are set to ones (11s).
<li>The mantissa of a floating-point value written to a floating-point register by floating-point instructions also appears in an MMX register.
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -