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<big><font face="黑体">INTEL 体系结构<br>MMX™ 技术程序员参考手册</font></big><br>
<small><FONT FACE="Arial"><b>Intel Architecture MMX™ Technology Programmer's Reference Manual</b></font></small><br><br>
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<h3><b>Chapter 3<BR>APPLICATION PROGRAMMING MODEL</b></h3>
This chapter describes the application programming environment as seen by compiler writers and assembly-language programmers. It also describes the architectural features which directly affect applications.
<H3><a name="3.1">3.1 DATA FORMATS</a></H3>
<H4><a name="3.1.1">3.1.1 Memory Data Formats</a></H4>
The Intel Architecture MMX™ technology introduces new packed data types, each 64 bits long. The data elements can be:
<ul>
<li>eight packed, consecutive 8-bit bytes
<li>four packed, consecutive 16-bit words
<li>two packed, consecutive 32-bit doublewords
</ul>
The 64 bits are numbered 0 through 63. Bit 0 is the least significant bit (LSB), and bit 63 is the most significant bit (MSB).<br><br>
The low-order bits are the lower part of the data element and the high-order bits are the upper part of the data element. For example, a word contains 16 bits numbered 0 through 15, the byte containing bits 0-7 of the word is called the low byte, and the byte containing bits 8-15 is called the high byte.<br><br>
Bytes in a multi-byte format have consecutive memory addresses. The ordering is always little endian. That is, the bytes with the lower addresses are less significant than the bytes with the higher addresses.<br><br>
<a name="Figure3-1"></a>
<CENTER><IMG SRC="3009000.gif" tppabs="http://freemind.163.net/database/mmx/3009000.gif" border=0></CENTER><br>
<CENTER><small>Figure 3-1. Eight Packed Bytes in Memory (at address 1000H)</small></CENTER>
<H4><a name="3.1.2">3.1.2 IA MMX™ Technology Register Data Formats</a></H4>
Values in IA MMX technology registers have the same format as a 64-bit quantity in memory. MMX technology registers have two data access modes: 64-bit access mode and 32-bit access mode.<br><br>
The 64-bit access mode is used for 64-bit memory access, 64-bit transfer between MMX technology registers, all pack, logical and arithmetic instructions, and some unpack instructions.<br><br>
The 32-bit access mode is used for 32-bit memory access, 32-bit transfer between integer registers and MMX technology registers, and some unpack instructions.
<H4><a name="3.1.3">3.1.3 IA MMX™ Technology Instructions and the Floating-Point Tag Word</a></H4>
After each MMX technology instruction, the entire floating-point tag word is set to Valid (00s). The Empty MMX Technology State (EMMS) instruction sets the entire floating-point tag word to Empty (11s).<br><br>
Section 4.3.2. describes the effects of floating-point and MMX technology instructions on the floating-point tag word. For details on floating-point tag word, refer to the <I>Pentium<sup>®</sup> Processor Family Developer's Manual</I>, Volume 3, Section 6.2.1.4.
<H3><a name="3.2">3.2 PREFIXES</a></H3>
Table 3-1 details the effect of a prefix on IA MMX Technology instructions.<br><br>
<a name="Table3-1"></a>
<center><table border="0" cellpadding="2" cellspacing="1" bgcolor="#EBDABE">
<TR><TD bgcolor="#000000" COLSPAN=2 WIDTH=524><CENTER><small><b>Table 3-1. IA MMX™ Technology Instruction Behavior with Prefixes Used by Application Programs</b></small></CENTER></TD></TR>
<TR><TD bgcolor="#000000" WIDTH=215><CENTER><small><B>Prefix Type</B></small></CENTER></TD><TD bgcolor="#000000" WIDTH=309><CENTER><small><B>The Effect of Prefix on IA MMX™ Technology Instructions </B></small></CENTER></TD></TR>
<TR><TD bgcolor="#000000" WIDTH=215><small>Address size (67H)</small></TD><TD bgcolor="#000000" WIDTH=309><small>Affects IA MMX technology instructions with a memory operand.<br>Ignored by IA MMX technology instructions without a memory operand.</small></TD></TR>
<TR><TD bgcolor="#000000" WIDTH=215><small>Operand size (66H)</small></TD><TD bgcolor="#000000" WIDTH=309><small>Ignored.</small></TD></TR>
<TR><TD bgcolor="#000000" WIDTH=215><small>Segment override</small></TD><TD bgcolor="#000000" WIDTH=309><small>Affects IA MMX technology instructions with a memory operand.<br>Ignored by IA MMX technology instructions without a memory operand.</small></TD></TR>
<TR><TD bgcolor="#000000" WIDTH=215><small>Repeat</small></TD><TD bgcolor="#000000" WIDTH=309><small>Ignored.</small></TD></TR>
<TR><TD bgcolor="#000000" WIDTH=215><small>Lock (F0H)</small></TD><TD bgcolor="#000000" WIDTH=309><small>Generates an invalid opcode exception.</small></TD></TR>
</TABLE></center>
<br>
See the <I>Pentium<sup>®</sup> Processor Family Developer's Manual</I>, Volume 3, Section 3.4. for information related to prefixes.
<H3><a name="3.3">3.3 WRITING APPLICATIONS WITH IA MMX™ TECHNOLOGY CODE</a></H3>
<H4><a name="3.3.1">3.3.1 Detecting IA MMX™ Technology Existence Using the CPUID Instruction</a></H4>
Use the CPUID instruction to determine whether the processor supports the IA MMX technology instruction set (refer to the <I>Pentium<sup>®</sup> Processor Family Developer's Manual</I>, Volume 3, Chapter 25, for more detail on the CPUID instruction). When the IA MMX technology support is detected by the CPUID instruction, it is signaled by setting bit 23 (IA MMX technology bit) in the feature flags to 1. In general, two versions of the routine can be created: one with scalar instructions and one with MMX technology instructions. The application will call the appropriate routine depending on the results of the CPUID instruction. If MMX technology support is detected, then the MMX technology routine is called; if no support for the MMX technology exists, the application calls the scalar routine.<br><br>
<blockquote>
<CENTER>NOTE</CENTER><br>
The CPUID instruction will continue to report the existence of the IA MMX technology if the CR0.EM bit is set (which signifies that the CPU is configured to generate exception Int 7 that can be used to emulate floating point instructions). In this case, executing an MMX technology instruction results in an invalid opcode exception.
</blockquote>
Example 3-1 illustrates how to use the CPUID instruction. This example does not represent the entire CPUID sequence, but shows the portion used for IA MMX technology detection.
<CENTER><H5><A NAME="X_ExampleOne">Example 3-1. Partial sequence of IA MMX™ technology detection by CPUID</A></H5></CENTER>
<pre>
... ; identify existence of CPUID instruction
...
... ; identify Intel processor
...
mov EAX, 1 ; request for feature flags
CPUID ; 0Fh, 0A2h CPUID instruction
test EDX, 00800000h ; Is IA MMX technology bit (Bit 23 of EDX)
; in feature flags set?
jnz MMX_Technology_Found
</pre>
<H4><a name="3.3.2">3.3.2 The EMMS Instruction</a></H4>
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