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<big><font face="黑体">INTEL 体系结构<br>MMX™ 技术程序员参考手册</font></big><br>
<small><FONT FACE="Arial"><b>Intel Architecture MMX™ Technology Programmer's Reference Manual</b></font></small><br><br>
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<h3><b>Chapter 5<BR>INTEL ARCHITECTURE MMX™ INSTRUCTION SET</b></h3>
This chapter presents the Intel Architecture MMX™ instructions in alphabetical order, with a full description of each instruction.<br><br>
The IA MMX technology defines fifty-seven new instructions. The instructions are grouped into the following functional categories:
<ul>
<li>Arithmetic Instructions
<li>Comparison Instructions
<li>Conversion Instructions
<li>Logical Instructions
<li>Shift Instructions
<li>Data Transfer Instructions
<li>Empty MMX State (EMMS) Instruction
</ul>
Appendix A summarizes the MMX instructions grouped by categories of related functions. Appendix B provides instruction formats and encodings, and Appendix C provides an alphabetical list of instruction mnemonics, their source data types, encodings in hexadecimal, and format. Appendix D provides an Opcode Map of the MMX instructions.<br><br>
Many of the instructions have multiple variations depending on the data types they support. Each variation has a different suffix. For example the PADD instruction has three variations: PADDB, PADDW, and PADDD, where the letters B, W, and D represent byte, word, and doubleword.
<H3><a name="5.1">5.1 INSTRUCTION SYNTAX</a></H3>
Instructions vary by:<br><br>
<ul>
<li>Data type: packed bytes, packed words, packed doublewords or quadwords
<li>Signed - Unsigned numbers
<li>Wraparound - Saturate arithmetic
</ul>
A typical MMX instruction has this syntax:
<ul>
<li>Prefix: <B>P</B> for Packed
<li>Instruction operation: for example - ADD, CMP, or XOR
<li>Suffix:<br>--<B>US</B> for Unsigned Saturation<br>--<B>S</B> for Signed saturation<br>--<B>B, W, D, Q</B> for the data type: packed byte, packed word, packed doubleword, or quadword.
</ul>
Instructions that have different input and output data elements have two data-type suffixes. For example, the conversion instruction converts from one data type to another. It has two suffixes: one for the original data type and the second for the converted data type.<br><br>
This is an example of an instruction mnemonic syntax:<br><br>
<ul>
<B>PADDUSW (Packed Add Unsigned with Saturation for Word)</B><br>
<B>P</B> = Packed<br>
<B>ADD</B> = the instruction operation<br>
<B>US</B> = Unsigned Saturation<br>
<B>W</B> = Word
</ul>
<H3><a name="5.2">5.2 INSTRUCTION FORMAT</a></H3>
The IA MMX instructions use the existing IA instruction format. All instructions, except the EMMS instruction, use the ModR/M format. All are preceded by the 0F prefix byte. For more details about the ModR/M format refer to <I>Pentium<sup>®</sup> Processor Family Developer's Manual Volume 3</I>, Section 25.2.1.<br><br>
For data-transfer instructions, the destination and source operands can reside in memory, integer registers, or MMX registers. For all other IA MMX instructions, the destination operands reside in MMX registers, and the source operands reside in memory, MMX registers, or immediate operands.<br><br>
All existing address modes are supported using the SIB (Scale Index Base) format.
<H3><a name="5.3">5.3 NOTATIONAL CONVENTIONS</a></H3>
The following conventions apply to all MMX instructions (except the EMMS instruction):
<ul>
<li>The instructions reference and operate on two operands: the source and destination operands. The right operand is the source and the left operand is the destination. The destination operand may also supply one of the inputs for the operation. The instruction overwrites the destination operand with the result.<br>
<li>When one of the operands is a memory location, the linear address corresponds to the address of the least significant byte of the referenced memory data.<br>
<li>The MMX instructions do not affect the condition flags.
</ul>
<H3><a name="5.4">5.4 HOW TO READ THE INSTRUCTION SET PAGES</a></H3>
The following is an example of the format used for each MMX instruction description in this chapter:<br><br>
<B>PSLL - Packed Shift Left Logical</B><br><br>
<center><table border="0" cellpadding="2" cellspacing="1" bgcolor="#EBDABE">
<TR><TD bgcolor="#000000" WIDTH=136><small><B>Opcode</small></B></TD><TD bgcolor="#000000" WIDTH=136><small><B>Instruction</small></B>
</TD><TD bgcolor="#000000" WIDTH=245><small><B>Description</small></B></TD>
</TR>
<TR><TD bgcolor="#000000" WIDTH=136><small>0F F1 /r</small></TD><TD bgcolor="#000000" WIDTH=136><small>PSLLW <I>mm, mm/m64</I></small>
</TD><TD bgcolor="#000000" WIDTH=245><small>Shift all words in MMX register to left by an amount specified in MMX register/memory, while shifting in zeros.</small>
</TD></TR>
</table></center>
<br>
The above table gives the instruction mnemonic and a brief description of the mnemonic. The columns content are explained below.<br><br>
<ul>
<B>Opcode Column</B><br><br>
The "Opcode" column provides the complete opcode produced for each form of the instruction.<br><br>
The codes are defined as hexadecimal bytes, in the same order in which they appear in memory. Definitions of entries other than hexadecimal bytes are as follows:<br><br>
<ul>
<li type=disc><B>/digit:</B> (digit is between 0 and 7) indicates that the ModR/M byte of the instruction uses only the r/m (register or memory) operand. The <B>reg</B> field contains the digit that provides a technology to the instruction's opcode.<br>
<li><B>/r</B>: indicates that the ModR/M byte of the instruction contains both a register operand and an r/m operand.<br>
<li><B>ib</B>: a 1-byte, immediate operand to the instruction that follows the opcode, ModR/M bytes, and scale-indexing bytes. The opcode determines if the operand is a signed value.<br><br>
</ul>
<B>Instruction Column</B><br><br>
The "Instruction" column contains the instruction syntax. The following is a list of the symbols used to represent operands in the instruction statements:<br><br>
<ul>
<li type=disc><B>imm8</B>: an immediate byte value, imm8 is a signed number between -128 and +127 inclusive.<br>
<li><B>r/m32</B>: a doubleword register or memory operand used for instructions whose operand-size attribute is 32 bits.<br>
<li><B>mm/m32</B>: indicates the lowest 32 bits of an MMX register or a 32-bit memory location.<br>
<li><B>mm/m64</B>: indicates a 64-bit MMX register or a 64-bit memory location.<br><br>
</ul>
<B>Description Column</B><br><br>
The "Description" column briefly explains the instruction activity.<br><br>
</ul>
<B>Operation</B><br><br>The "Operation" section contains an algorithmic description of the operation performed by the instruction.<br><br>
The register name or memory location implies the contents of the register or memory.<br><br>
The bit values are written from high-order to low-order and indicate the address within the register or memory. The bit addresses are specified along with the register name or memory location in brackets. For example mm(7..0) represents the low-order 8 bits in an MMX register.<br><br>
The algorithms are composed of the following elements:<br><br>
<ul>
<li type=disc>Comments are enclosed with the symbol pairs "(*" and "*)".<br>
<li>Compound statements are enclosed between the keywords of the "if" statement (IF, THEN, ELSE).<br>
<li>A<--B; indicates that the value of B is assigned to A.<br>
<li>The symbols =, <>, >, <, , and are relational operators used to compare two values, meaning equal, not equal, greater or equal, less or equal, respectively. A relational expression such as A=B is TRUE if the value for A is equal to B; otherwise it is FALSE.<br><br>
</ul>
The following functions are used in the algorithmic descriptions:<br><br>
<ul>
<li type=disc><B>ZeroExtend (value)</B> returns a value zero-extended to the operand-size attribute of the instruction. For example, if OperandSize = 32, ZeroExtend of a byte value of -10 converts the byte from F6H to doubleword with hexadecimal value 000000F6H. If the value passed to ZeroExtend and the operand-size attribute are the same size, ZeroExtend returns the value unaltered.<br>
<li><B>SignExtend (value)</B> returns a value sign-extended to the operand-size attribute of the instruction. For example, if OperandSize = 32, SignExtend of a byte containing the value -10 converts the byte from F6H to doubleword with hexadecimal value FFFFFFF6H. If the value passed to SignExtend and the operand-size attribute are the same size, SignExtend returns the value unaltered.<br>
<li><B>SaturateSignedWordToSignedByte</B> converts a signed 16-bit value to a signed 8-bit value. If the signed 16-bit value is less than -128, it is represented by the saturated value -128 (0x80). If it is greater than 127, it is represented by the saturated value 127 (0x7F).<br>
<li><B>SaturateSignedDwordToSignedWord</B> converts a signed 32-bit value to a signed 16-bit value. If the signed 32-bit value is less than -32768, it is represented by the saturated value -32768 (0x8000). If it is greater than 32767, it is represented by the saturated value 32767 (0x7FFF).<br>
<li><B>SaturateSignedWordToUnsignedByte</B> converts a signed 16-bit value to an unsigned 8­bit value. If the signed 16-bit value is less than zero it is represented by the saturated value zero (0x00).If it is greater than 255 it is represented by the saturated value 255 (0xFF).<br>
<li><B>SaturateToSignedByte </B>represents the result of an operation as a signed 8-bit value. If the result is less than -128, it is represented by the saturated value -128 (0x80). If it is greater than 127, it is represented by the saturated value 127 (0x7F).<br>
<li><B>SaturateToSignedWord</B> represents the result of an operation as a signed 16-bit value. If the result is less than -32768, it is represented by the saturated value -32768 (0x8000). If it is greater than 32767, it is represented by the saturated value 32767 (0x7FFF).<br>
<li><B>SaturateToUnsignedByte</B> represents the result of an operation as a signed 8-bit value. If the result is less than zero it is represented by the saturated value zero (0x00). If it is greater than 255, it is represented by the saturated value 255 (0xFF).<br>
<li><B>SaturateToUnsignedWord</B> represents the result of an operation as a signed 16-bit value. If the result is less than zero it is represented by the saturated value zero (0x00).I If it is greater than 65535, it is represented by the saturated value 65535 (0xFFFF).<br><br>
</ul>
<B>Description</B><br><br>
The "Description" section describes the operation for all variations of the instruction.<br><br>
<B>Example</B><br><br>
The "Example" section contains a graphical representation of the instruction's functional behavior.<br><br>
<B>Exceptions</B><br><br>
The "Exceptions" section lists the exceptions in the three different modes: Protected mode, Real Address mode, and Virtual-8086 mode.<br><br>
Refer to Section 4.2 of this document for more detail on these exceptions. See also the <I>Pentium<sup>®</sup> Processor Family Manual, Volume 3</I>, Section 9.4 and Chapter 14.<br><br>
<table border="0" width="100%"><tr><td bgcolor="#CBBA9E" height="1"></td></tr></table>
<H5><a name="EMMS">EMMS - Empty MMX™ State</a></H5>
<center><table border="0" cellpadding="2" cellspacing="1" bgcolor="#EBDABE">
<TR><TD bgcolor="#000000" WIDTH=103><small><B>Opcode</small></B></TD><TD bgcolor="#000000" WIDTH=120><small><B>Instruction</small></B>
</TD><TD bgcolor="#000000" WIDTH=288><small><B>Description</small></B></TD>
</TR>
<TR><TD bgcolor="#000000" WIDTH=103><small>0F 77</small></TD><TD bgcolor="#000000" WIDTH=120><small>EMMS</small>
</TD><TD bgcolor="#000000" WIDTH=288><small>Set the FP tag word to empty.</small>
</TD></TR>
</table></center>
<br>
<B>Operation</B><br><br>
TW<--0xFFFF;<br><br>
<B>Description</B><br><br>
The EMMS instruction sets the values of the floating-point (FP) tag word to empty (all ones). EMMS marks the registers as available, so they can subsequently be used by floating-point instructions.<br><br>
If a floating-point instruction loads into one of the registers before it has been reset by the EMMS instruction, a floating-point stack overflow can occur, which results in an FP exception or incorrect result.<br><br>
All other MMX instructions validate the entire FP tag word (all zeros).<br><br>
<CENTER>NOTE</CENTER>
<blockquote>This instruction must be used to clear the MMX state at the end of all MMX routines, and before calling other routines that may execute floating-point instructions.</blockquote>
Figure 5-1 shows the format of the FP Tag Word.<br><br>
<a name="Figure5-1"></a>
<CENTER><IMG SRC="3006047.gif" tppabs="http://freemind.163.net/database/mmx/3006047.gif" border=0></CENTER>
<br><CENTER><small>Figure 5-1. Floating Point Tag Word Format</small></CENTER><br>
<B>Flags Affected</B><br><br>
None.<br><br>
<B>Protected Mode Exceptions</B><br><br>
#UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #MF if there is a pending FPU exception.<br><br>
<B>Real Address Mode Exceptions</B><br><br>
#UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #MF if there is a pending FPU exception.<br><br>
<B>Virtual 8086 Mode Exceptions</B><br><br>
#UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #MF if there is a pending FPU exception.<br><br>
<table border="0" width="100%"><tr><td bgcolor="#CBBA9E" height="1"></td></tr></table>
<H5><a name="MOVD">MOVD - Move 32 Bits</a></H5>
<center><table border="0" cellpadding="2" cellspacing="1" bgcolor="#EBDABE">
<TR><TD bgcolor="#000000" WIDTH=103><small><B>Opcode</small></B></TD><TD bgcolor="#000000" WIDTH=120><small><B>Instruction</small></B>
</TD><TD bgcolor="#000000" WIDTH=288><small><B>Description</small></B></TD>
</TR>
<TR><TD bgcolor="#000000" WIDTH=103><small>0F 6E /r</small></TD><TD bgcolor="#000000" WIDTH=120><small>MOVD <I>mm, r/m32</I></small>
</TD><TD bgcolor="#000000" WIDTH=288><small>Move 32 bits from integer register/memory to MMX register.</small>
</TD></TR>
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