altsyncram_rd31.tdf

基于VHDL+FPGA的DDS信号发生设计

--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone" ENABLE_RUNTIME_MOD="NO" INIT_FILE="romdata.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=4096 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=4096 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 7.1 cbx_altsyncram 2007:03:22:08:29:24:SJ cbx_cycloneii 2007:01:23:09:39:40:SJ cbx_lpm_add_sub 2007:01:08:11:15:18:SJ cbx_lpm_compare 2007:02:05:11:33:54:SJ cbx_lpm_decode 2006:11:21:10:27:00:SJ cbx_lpm_mux 2006:11:21:10:27:10:SJ cbx_mgl 2007:04:03:14:06:46:SJ cbx_stratix 2007:04:12:16:43:52:SJ cbx_stratixii 2007:02:12:17:08:26:SJ cbx_stratixiii 2007:03:13:14:47:12:SJ cbx_util_mgl 2007:01:15:12:22:48:SJ  VERSION_END


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--synthesis_resources = 
SUBDESIGN altsyncram_rd31
( 
	address_a[4095..0]	:	input;
	clock0	:	input;
	q_a[15..0]	:	output;
) 

BEGIN 
	ASSERT (0) 
	REPORT "Cannot implement altsyncram megafunction because RAM size is too large to use with OPERATION_MODE parameter set to value ROM"
	SEVERITY ERROR;
	ASSERT (0) 
	REPORT "Insufficient address lines in altsyncram megafunction design -- 4096 memory words in side A specified but total number of address lines is 4096"
	SEVERITY ERROR;
END;
--ERROR FILE