dds.hier_info

基于VHDL+FPGA的DDS信号发生设计

|dds
clk => rom:u2.clock
clk => add_phase:u1.clk
fctro[0] => add_phase:u1.fc[0]
fctro[1] => add_phase:u1.fc[1]
fctro[2] => add_phase:u1.fc[2]
fctro[3] => add_phase:u1.fc[3]
fctro[4] => add_phase:u1.fc[4]
fctro[5] => add_phase:u1.fc[5]
fctro[6] => add_phase:u1.fc[6]
fctro[7] => add_phase:u1.fc[7]
fctro[8] => add_phase:u1.fc[8]
fctro[9] => add_phase:u1.fc[9]
fctro[10] => add_phase:u1.fc[10]
fctro[11] => add_phase:u1.fc[11]
fctro[12] => add_phase:u1.fc[12]
fctro[13] => add_phase:u1.fc[13]
fctro[14] => add_phase:u1.fc[14]
fctro[15] => add_phase:u1.fc[15]
addout[0] <= rom:u2.q[0]
addout[1] <= rom:u2.q[1]
addout[2] <= rom:u2.q[2]
addout[3] <= rom:u2.q[3]
addout[4] <= rom:u2.q[4]
addout[5] <= rom:u2.q[5]
addout[6] <= rom:u2.q[6]
addout[7] <= rom:u2.q[7]
addout[8] <= rom:u2.q[8]
addout[9] <= rom:u2.q[9]
addout[10] <= rom:u2.q[10]
addout[11] <= rom:u2.q[11]
addout[12] <= rom:u2.q[12]
addout[13] <= rom:u2.q[13]
addout[14] <= rom:u2.q[14]
addout[15] <= rom:u2.q[15]


|dds|add_phase:u1
clk => phase[15].CLK
clk => phase[14].CLK
clk => phase[13].CLK
clk => phase[12].CLK
clk => phase[11].CLK
clk => phase[10].CLK
clk => phase[9].CLK
clk => phase[8].CLK
clk => phase[7].CLK
clk => phase[6].CLK
clk => phase[5].CLK
clk => phase[4].CLK
clk => phase[3].CLK
clk => phase[2].CLK
clk => phase[1].CLK
clk => phase[0].CLK
clk => adderss[15]~reg0.CLK
clk => adderss[14]~reg0.CLK
clk => adderss[13]~reg0.CLK
clk => adderss[12]~reg0.CLK
clk => adderss[11]~reg0.CLK
clk => adderss[10]~reg0.CLK
clk => adderss[9]~reg0.CLK
clk => adderss[8]~reg0.CLK
clk => adderss[7]~reg0.CLK
clk => adderss[6]~reg0.CLK
clk => adderss[5]~reg0.CLK
clk => adderss[4]~reg0.CLK
clk => adderss[3]~reg0.CLK
clk => adderss[2]~reg0.CLK
clk => adderss[1]~reg0.CLK
clk => adderss[0]~reg0.CLK
fc[0] => Add0.IN16
fc[1] => Add0.IN15
fc[2] => Add0.IN14
fc[3] => Add0.IN13
fc[4] => Add0.IN12
fc[5] => Add0.IN11
fc[6] => Add0.IN10
fc[7] => Add0.IN9
fc[8] => Add0.IN8
fc[9] => Add0.IN7
fc[10] => Add0.IN6
fc[11] => Add0.IN5
fc[12] => Add0.IN4
fc[13] => Add0.IN3
fc[14] => Add0.IN2
fc[15] => Add0.IN1
adderss[0] <= adderss[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adderss[1] <= adderss[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adderss[2] <= adderss[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adderss[3] <= adderss[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adderss[4] <= adderss[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adderss[5] <= adderss[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adderss[6] <= adderss[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adderss[7] <= adderss[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adderss[8] <= adderss[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adderss[9] <= adderss[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adderss[10] <= adderss[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adderss[11] <= adderss[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adderss[12] <= adderss[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adderss[13] <= adderss[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adderss[14] <= adderss[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adderss[15] <= adderss[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|dds|rom:u2
clock => altsyncram:altsyncram_component.clock0
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
address[8] => altsyncram:altsyncram_component.address_a[8]
address[9] => altsyncram:altsyncram_component.address_a[9]
address[10] => altsyncram:altsyncram_component.address_a[10]
address[11] => altsyncram:altsyncram_component.address_a[11]
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]
q[8] <= altsyncram:altsyncram_component.q_a[8]
q[9] <= altsyncram:altsyncram_component.q_a[9]
q[10] <= altsyncram:altsyncram_component.q_a[10]
q[11] <= altsyncram:altsyncram_component.q_a[11]
q[12] <= altsyncram:altsyncram_component.q_a[12]
q[13] <= altsyncram:altsyncram_component.q_a[13]
q[14] <= altsyncram:altsyncram_component.q_a[14]
q[15] <= altsyncram:altsyncram_component.q_a[15]


|dds|rom:u2|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_a[12] => ~NO_FANOUT~
data_a[13] => ~NO_FANOUT~
data_a[14] => ~NO_FANOUT~
data_a[15] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_5i31:auto_generated.address_a[0]
address_a[1] => altsyncram_5i31:auto_generated.address_a[1]
address_a[2] => altsyncram_5i31:auto_generated.address_a[2]
address_a[3] => altsyncram_5i31:auto_generated.address_a[3]
address_a[4] => altsyncram_5i31:auto_generated.address_a[4]
address_a[5] => altsyncram_5i31:auto_generated.address_a[5]
address_a[6] => altsyncram_5i31:auto_generated.address_a[6]
address_a[7] => altsyncram_5i31:auto_generated.address_a[7]
address_a[8] => altsyncram_5i31:auto_generated.address_a[8]
address_a[9] => altsyncram_5i31:auto_generated.address_a[9]
address_a[10] => altsyncram_5i31:auto_generated.address_a[10]
address_a[11] => altsyncram_5i31:auto_generated.address_a[11]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_5i31:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_5i31:auto_generated.q_a[0]
q_a[1] <= altsyncram_5i31:auto_generated.q_a[1]
q_a[2] <= altsyncram_5i31:auto_generated.q_a[2]
q_a[3] <= altsyncram_5i31:auto_generated.q_a[3]
q_a[4] <= altsyncram_5i31:auto_generated.q_a[4]
q_a[5] <= altsyncram_5i31:auto_generated.q_a[5]
q_a[6] <= altsyncram_5i31:auto_generated.q_a[6]
q_a[7] <= altsyncram_5i31:auto_generated.q_a[7]
q_a[8] <= altsyncram_5i31:auto_generated.q_a[8]
q_a[9] <= altsyncram_5i31:auto_generated.q_a[9]
q_a[10] <= altsyncram_5i31:auto_generated.q_a[10]
q_a[11] <= altsyncram_5i31:auto_generated.q_a[11]
q_a[12] <= altsyncram_5i31:auto_generated.q_a[12]
q_a[13] <= altsyncram_5i31:auto_generated.q_a[13]
q_a[14] <= altsyncram_5i31:auto_generated.q_a[14]
q_a[15] <= altsyncram_5i31:auto_generated.q_a[15]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|dds|rom:u2|altsyncram:altsyncram_component|altsyncram_5i31:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR