dds.map.qmsg

基于VHDL+FPGA的DDS信号发生设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 01 16:34:06 2008 " "Info: Processing started: Wed Oct 01 16:34:06 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dds -c dds " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dds -c dds" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file dds.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 my_copponent " "Info: Found design unit 1: my_copponent" {  } { { "dds.vhd" "" { Text "F:/desige/dds/dds.vhd" 5 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 dds-dds " "Info: Found design unit 2: dds-dds" {  } { { "dds.vhd" "" { Text "F:/desige/dds/dds.vhd" 34 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 dds " "Info: Found entity 1: dds" {  } { { "dds.vhd" "" { Text "F:/desige/dds/dds.vhd" 27 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add_phase.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file add_phase.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 add_phase-add_phase " "Info: Found design unit 1: add_phase-add_phase" {  } { { "add_phase.vhd" "" { Text "F:/desige/dds/add_phase.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 add_phase " "Info: Found entity 1: add_phase" {  } { { "add_phase.vhd" "" { Text "F:/desige/dds/add_phase.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dds " "Info: Elaborating entity \"dds\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_phase add_phase:u1 " "Info: Elaborating entity \"add_phase\" for hierarchy \"add_phase:u1\"" {  } { { "dds.vhd" "u1" { Text "F:/desige/dds/dds.vhd" 38 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "rom.vhd 2 1 " "Warning: Using design file rom.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rom-SYN " "Info: Found design unit 1: rom-SYN" {  } { { "rom.vhd" "" { Text "F:/desige/dds/rom.vhd" 53 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 rom " "Info: Found entity 1: rom" {  } { { "rom.vhd" "" { Text "F:/desige/dds/rom.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom rom:u2 " "Info: Elaborating entity \"rom\" for hierarchy \"rom:u2\"" {  } { { "dds.vhd" "u2" { Text "F:/desige/dds/dds.vhd" 40 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom:u2\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"rom:u2\|altsyncram:altsyncram_component\"" {  } { { "rom.vhd" "altsyncram_component" { Text "F:/desige/dds/rom.vhd" 84 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "rom:u2\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"rom:u2\|altsyncram:altsyncram_component\"" {  } { { "rom.vhd" "" { Text "F:/desige/dds/rom.vhd" 84 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_5i31.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_5i31.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_5i31 " "Info: Found entity 1: altsyncram_5i31" {  } { { "db/altsyncram_5i31.tdf" "" { Text "F:/desige/dds/db/altsyncram_5i31.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_5i31 rom:u2\|altsyncram:altsyncram_component\|altsyncram_5i31:auto_generated " "Info: Elaborating entity \"altsyncram_5i31\" for hierarchy \"rom:u2\|altsyncram:altsyncram_component\|altsyncram_5i31:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "77 " "Info: Implemented 77 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "17 " "Info: Implemented 17 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "28 " "Info: Implemented 28 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_RAMS" "16 " "Info: Implemented 16 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "151 " "Info: Allocated 151 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 01 16:34:10 2008 " "Info: Processing ended: Wed Oct 01 16:34:10 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}